More stuff
This commit is contained in:
parent
9f111fde11
commit
4613bcddab
181
avr.instr.tex
181
avr.instr.tex
@ -53,14 +53,30 @@
|
||||
}
|
||||
|
||||
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
% Helpers
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
|
||||
% ADD -- Add without Carry
|
||||
\def\avr@instr@ADD#1#2#3{% ADD PC, Rd, Rr, PC
|
||||
\avr@bin@msb@del{#2}{\avr@ADD@dddd}{\avr@ADD@d}%
|
||||
\avr@bin@msb@del{#3}{\avr@ADD@rrrr}{\avr@ADD@r}%
|
||||
\avr@code@set{000011\avr@ADD@r\avr@ADD@d\avr@ADD@dddd\avr@ADD@rrrr}{#1}%
|
||||
\def\avr@instr@gen@tworegs#1#2#3#4{%
|
||||
\avr@bin@msb@del{#3}{\avr@ADD@dddd}{\avr@ADD@d}%
|
||||
\avr@bin@msb@del{#4}{\avr@ADD@rrrr}{\avr@ADD@r}%
|
||||
\avr@code@set{#1\avr@ADD@r\avr@ADD@d\avr@ADD@dddd\avr@ADD@rrrr}{#2}%
|
||||
}
|
||||
|
||||
\def\avr@instr@gen@regconst#1#2#3#4{%
|
||||
\avr@bin@msb@del{#3}{\avr@LDI@dddd}{\avr@LDI@d}%
|
||||
\avr@bin@nibble@high{#4}{\avr@LDI@H}%
|
||||
\avr@bin@nibble@low{#4}{\avr@LDI@L}%
|
||||
\avr@code@set{#1\avr@LDI@H\avr@LDI@dddd\avr@LDI@L}{#2}%
|
||||
}
|
||||
|
||||
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
% Arithmetic instructions
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
% ADD -- Add without Carry
|
||||
\def\avr@instr@ADD{\avr@instr@gen@tworegs{000011}}
|
||||
|
||||
\csdef{avr@instr@000011}#1#2#3#4#5#6#7\@nnil{%
|
||||
\def\avr@instr@extracarry{0}%
|
||||
\avr@reg@get{#1#7}{\avr@Rr}%
|
||||
@ -74,12 +90,7 @@
|
||||
}
|
||||
|
||||
% ADC -- Add with Carry
|
||||
\def\avr@instr@ADC#1#2#3{% ADC PC, Rd, Rr, PC
|
||||
\avr@bin@msb@del{#2}{\avr@ADD@dddd}{\avr@ADD@d}%
|
||||
\avr@bin@msb@del{#3}{\avr@ADD@rrrr}{\avr@ADD@r}%
|
||||
\avr@code@set{000111\avr@ADD@r\avr@ADD@d\avr@ADD@dddd\avr@ADD@rrrr}{#1}%
|
||||
}
|
||||
|
||||
\def\avr@instr@ADC{\avr@instr@gen@tworegs{000111}}
|
||||
|
||||
\csdef{avr@instr@000111}#1#2#3#4#5#6#7\@nnil{%
|
||||
\avr@reg@get{#1#7}{\avr@Rr}%
|
||||
@ -95,13 +106,7 @@
|
||||
}
|
||||
|
||||
% SUB -- Substract without carry
|
||||
|
||||
\def\avr@instr@SUB#1#2#3{% SUB PC, Rd, Rr, PC
|
||||
\avr@bin@msb@del{#2}{\avr@ADD@dddd}{\avr@ADD@d}%
|
||||
\avr@bin@msb@del{#3}{\avr@ADD@rrrr}{\avr@ADD@r}%
|
||||
\avr@code@set{000110\avr@ADD@r\avr@ADD@d\avr@ADD@dddd\avr@ADD@rrrr}{#1}%
|
||||
}
|
||||
|
||||
\def\avr@instr@SUB{\avr@instr@gen@tworegs{000110}}
|
||||
\csdef{avr@instr@000110}#1#2#3#4#5#6#7\@nnil{%
|
||||
\avr@reg@get{#1#7}{\avr@Rr}%
|
||||
\avr@reg@get{#2#3#4#5#6}{\avr@Rd}%
|
||||
@ -115,12 +120,7 @@
|
||||
\avr@pc@inc%
|
||||
}
|
||||
% SBC - Substract with Carry
|
||||
\def\avr@instr@SBC#1#2#3{% SBC PC, Rd, Rr, PC
|
||||
\avr@bin@msb@del{#2}{\avr@ADD@dddd}{\avr@ADD@d}%
|
||||
\avr@bin@msb@del{#3}{\avr@ADD@rrrr}{\avr@ADD@r}%
|
||||
\avr@code@set{000010\avr@ADD@r\avr@ADD@d\avr@ADD@dddd\avr@ADD@rrrr}{#1}%
|
||||
}
|
||||
|
||||
\def\avr@instr@SBC{\avr@instr@gen@tworegs{000010}}
|
||||
\csdef{avr@instr@000010}#1#2#3#4#5#6#7\@nnil{%
|
||||
\avr@reg@get{#1#7}{\avr@Rr}%
|
||||
\avr@reg@get{#2#3#4#5#6}{\avr@Rd}%
|
||||
@ -135,13 +135,38 @@
|
||||
\avr@pc@inc%
|
||||
}
|
||||
|
||||
% CP -- Compare without Carry
|
||||
\def\avr@instr@CP#1#2#3{% CP PC, Rd, Rr, PC
|
||||
\avr@bin@msb@del{#2}{\avr@ADD@dddd}{\avr@ADD@d}%
|
||||
\avr@bin@msb@del{#3}{\avr@ADD@rrrr}{\avr@ADD@r}%
|
||||
\avr@code@set{000101\avr@ADD@r\avr@ADD@d\avr@ADD@dddd\avr@ADD@rrrr}{#1}%
|
||||
% SUBI - Substract Immediate
|
||||
\def\avr@instr@SUBI{\avr@instr@gen@regconst{0101}}
|
||||
\csdef{avr@instr@0101}#1#2#3#4#5#6#7#8#9\@nnil{%
|
||||
\avr@reg@get{1#5#6#7#8}{\avr@Rd}%
|
||||
\def\avr@Rr{#1#2#3#4#9}%
|
||||
\def\avr@instr@extracarry{1}%
|
||||
\avr@debug{SUBI - \%#2#3#4#5#6 <- #2#3#4#5#6(=\avr@Rd) - \avr@Rr}%
|
||||
\def\avr@instr@adder@RrPreprocess{\avr@bit@negate}%
|
||||
\csuse{avr@instr@adder@helper}%
|
||||
% Set the result register
|
||||
\avr@reg@set{\avr@Rx}{1#5#6#7#8}%
|
||||
\avr@pc@inc%
|
||||
}
|
||||
|
||||
% SBCI - Substract Immediate
|
||||
\def\avr@instr@SBCI{\avr@instr@gen@regconst{0100}}
|
||||
\csdef{avr@instr@0100}#1#2#3#4#5#6#7#8#9\@nnil{%
|
||||
\avr@reg@get{1#5#6#7#8}{\avr@Rd}%
|
||||
\def\avr@Rr{#1#2#3#4#9}%
|
||||
\avr@flag@get C \@@carry%
|
||||
\xdef \avr@instr@extracarry {\avr@bit@negate \@@carry}%
|
||||
\avr@debug{SBCI - \%#2#3#4#5#6 <- #2#3#4#5#6(=\avr@Rd) - \avr@Rr -\@@carry}%
|
||||
\def\avr@instr@adder@RrPreprocess{\avr@bit@negate}%
|
||||
\csuse{avr@instr@adder@helper}%
|
||||
% Set the result register
|
||||
\avr@reg@set{\avr@Rx}{1#5#6#7#8}%
|
||||
\avr@pc@inc%
|
||||
}
|
||||
|
||||
% CP -- Compare without Carry
|
||||
\def\avr@instr@CP{\avr@instr@gen@tworegs{000101}}
|
||||
|
||||
\csdef{avr@instr@000101}#1#2#3#4#5#6#7\@nnil{%
|
||||
\avr@reg@get{#1#7}{\avr@Rr}%
|
||||
\avr@reg@get{#2#3#4#5#6}{\avr@Rd}%
|
||||
@ -154,11 +179,7 @@
|
||||
}
|
||||
|
||||
% CPC -- Compare with Carry
|
||||
\def\avr@instr@CPC#1#2#3{% CPC PC, Rd, Rr, PC
|
||||
\avr@bin@msb@del{#2}{\avr@ADD@dddd}{\avr@ADD@d}%
|
||||
\avr@bin@msb@del{#3}{\avr@ADD@rrrr}{\avr@ADD@r}%
|
||||
\avr@code@set{000001\avr@ADD@r\avr@ADD@d\avr@ADD@dddd\avr@ADD@rrrr}{#1}%
|
||||
}
|
||||
\def\avr@instr@CPC{\avr@instr@gen@tworegs{000001}}
|
||||
|
||||
\csdef{avr@instr@000001}#1#2#3#4#5#6#7\@nnil{%
|
||||
\avr@reg@get{#1#7}{\avr@Rr}%
|
||||
@ -216,13 +237,8 @@
|
||||
}
|
||||
|
||||
% LDI -- Load Immediate Value
|
||||
\def\avr@instr@LDI#1#2#3{% LDI PC, Rd, K
|
||||
\avr@bin@msb@del{#2}{\avr@LDI@dddd}{\avr@LDI@d}%
|
||||
\avr@bin@nibble@high{#3}{\avr@LDI@H}%
|
||||
\avr@bin@nibble@low{#3}{\avr@LDI@L}%
|
||||
\avr@code@set{1110\avr@LDI@H\avr@LDI@dddd\avr@LDI@L}{#1}%
|
||||
}
|
||||
|
||||
\def\avr@instr@LDI{\avr@instr@gen@regconst{1110}}
|
||||
\def\avr@instr@SER#1#2{\avr@instr@gen@regconst{1110}{#1}{#2}{11111111}}
|
||||
\csdef{avr@instr@1110}#1#2#3#4#5#6#7#8#9\@nnil{%
|
||||
\avr@debug{LDI - \%1#5#6#7#8 <- #1#2#3#4#9}%
|
||||
\avr@reg@set{#1#2#3#4#9}{1#5#6#7#8}%
|
||||
@ -367,11 +383,7 @@
|
||||
% Data transfert instructions
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
% MOV
|
||||
\def\avr@instr@MOV#1#2#3{% CP PC, Rd, Rr
|
||||
\avr@bin@msb@del{#2}{\avr@ADD@dddd}{\avr@ADD@d}%
|
||||
\avr@bin@msb@del{#3}{\avr@ADD@rrrr}{\avr@ADD@r}%
|
||||
\avr@code@set{001011\avr@ADD@r\avr@ADD@d\avr@ADD@dddd\avr@ADD@rrrr}{#1}%
|
||||
}
|
||||
\def\avr@instr@MOV{\avr@instr@gen@tworegs{001011}}
|
||||
|
||||
\csdef{avr@instr@001011}#1#2#3#4#5#6#7\@nnil{%
|
||||
\avr@reg@get{#1#7}{\avr@Rr}%
|
||||
@ -393,6 +405,83 @@
|
||||
\avr@pc@inc%
|
||||
}
|
||||
|
||||
\def\avr@instr@NOP#1{% BREAK PC
|
||||
\avr@code@set{0000000000000000}{#1}%
|
||||
}
|
||||
|
||||
\csdef{avr@instr@0000000000000000}\@nnil{%
|
||||
\avr@debug{NOP}%
|
||||
\avr@pc@inc%
|
||||
}
|
||||
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
% Logical Instructions
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
\def\avr@instr@bitop@helper{%
|
||||
\avr@debug{\avr@instr@bitop - {\avr@Rd} AND {\avr@Rr}}%
|
||||
\csuse{avr@bin@\avr@instr@bitop}{\avr@Rr}{\avr@Rd}{\avr@Rx}%
|
||||
\avr@flag@set V 0%
|
||||
\avr@flags@update \avr@Rx%
|
||||
}
|
||||
|
||||
\def\avr@instr@AND{\avr@instr@gen@tworegs{001000}}
|
||||
\def\avr@instr@TST#1#2{\avr@instr@gen@tworegs{001000}{#1}{#2}{#2}}
|
||||
\csdef{avr@instr@001000}#1#2#3#4#5#6#7\@nnil{%
|
||||
\avr@reg@get{#1#7}{\avr@Rr}%
|
||||
\avr@reg@get{#2#3#4#5#6}{\avr@Rd}%
|
||||
\def\avr@instr@bitop{and}%
|
||||
\avr@instr@bitop@helper%
|
||||
% Set the result register
|
||||
\avr@reg@set{\avr@Rx}{#2#3#4#5#6}%
|
||||
\avr@pc@inc%
|
||||
}
|
||||
|
||||
\def\avr@instr@ANDI{\avr@instr@gen@regconst{0111}}
|
||||
\csdef{avr@instr@0111}#1#2#3#4#5#6#7#8#9\@nnil{%
|
||||
\avr@reg@get{1#5#6#7#8}{\avr@Rd}%
|
||||
\def\avr@Rr{#1#2#3#4#9}%
|
||||
\def\avr@instr@bitop{and}%
|
||||
\avr@instr@bitop@helper%
|
||||
% Set the result register
|
||||
\avr@reg@set{\avr@Rx}{1#5#6#7#8}%
|
||||
\avr@pc@inc%
|
||||
}
|
||||
|
||||
|
||||
\def\avr@instr@OR{\avr@instr@gen@tworegs{001010}}
|
||||
\csdef{avr@instr@001010}#1#2#3#4#5#6#7\@nnil{%
|
||||
\avr@reg@get{#1#7}{\avr@Rr}%
|
||||
\avr@reg@get{#2#3#4#5#6}{\avr@Rd}%
|
||||
\def\avr@instr@bitop{or}%
|
||||
\avr@instr@bitop@helper%
|
||||
% Set the result register
|
||||
\avr@reg@set{\avr@Rx}{#2#3#4#5#6}%
|
||||
\avr@pc@inc%
|
||||
}
|
||||
|
||||
\def\avr@instr@ORI{\avr@instr@gen@regconst{0110}}
|
||||
\csdef{avr@instr@0110}#1#2#3#4#5#6#7#8#9\@nnil{%
|
||||
\avr@reg@get{1#5#6#7#8}{\avr@Rd}%
|
||||
\def\avr@Rr{#1#2#3#4#9}%
|
||||
\def\avr@instr@bitop{or}%
|
||||
\avr@instr@bitop@helper%
|
||||
% Set the result register
|
||||
\avr@reg@set{\avr@Rx}{1#5#6#7#8}%
|
||||
\avr@pc@inc%
|
||||
}
|
||||
|
||||
\def\avr@instr@EOR{\avr@instr@gen@tworegs{001001}}
|
||||
\def\avr@instr@CLR#1#2{\avr@instr@EOR{#1}{#2}{#2}}
|
||||
\csdef{avr@instr@001001}#1#2#3#4#5#6#7\@nnil{%
|
||||
\avr@reg@get{#1#7}{\avr@Rr}%
|
||||
\avr@reg@get{#2#3#4#5#6}{\avr@Rd}%
|
||||
\def\avr@instr@bitop{xor}%
|
||||
\avr@instr@bitop@helper%
|
||||
% Set the result register
|
||||
\avr@reg@set{\avr@Rx}{#2#3#4#5#6}%
|
||||
\avr@pc@inc%
|
||||
}
|
||||
|
||||
|
||||
|
||||
%%% Local Variables:
|
||||
|
@ -172,6 +172,46 @@
|
||||
}
|
||||
\preto\avr@test{\avr@test@fibonacci}
|
||||
|
||||
\def\avr@test@BITOPS{%
|
||||
\avr@test@setup{Bit Operations}%
|
||||
\avr@instr@LDI{0}{\csuse{avr@r30}}{00111100}%
|
||||
\avr@instr@LDI{1}{\csuse{avr@r31}}{00001111}%
|
||||
\avr@instr@AND{2}{\csuse{avr@r30}}{\csuse{avr@r31}}%
|
||||
|
||||
\avr@instr@stepn{3}%
|
||||
\avr@test@REG{r30}{00001100}
|
||||
|
||||
\avr@instr@ANDI{3}{\csuse{avr@r30}}{00001000}%
|
||||
\avr@instr@stepn{1}%
|
||||
\avr@test@REG{r30}{00001000}
|
||||
|
||||
\avr@instr@ORI{4}{\csuse{avr@r20}}{10101010}%
|
||||
\avr@instr@stepn{1}%
|
||||
\avr@test@REG{r20}{10101010}
|
||||
|
||||
\avr@instr@EOR{5}{\csuse{avr@r30}}{\csuse{avr@r20}}%
|
||||
\avr@instr@TST{6}{\csuse{avr@r30}}%
|
||||
\avr@instr@stepn{2}%
|
||||
\avr@test@REG{r30}{10100010}
|
||||
}
|
||||
\preto\avr@test{\avr@test@BITOPS}
|
||||
|
||||
\def\avr@test@SUBI{%
|
||||
\avr@test@setup{SUBI}%
|
||||
\avr@instr@LDI{0}{\csuse{avr@r30}}{00001111}%
|
||||
\avr@instr@SUBI{1}{\csuse{avr@r30}}{00010000}%
|
||||
\avr@instr@SBCI{2}{\csuse{avr@r30}}{00000001}%
|
||||
|
||||
\avr@instr@stepn{2}%
|
||||
\avr@test@REG{r30}{11111111}
|
||||
\avr@test@SREG{00000101}
|
||||
|
||||
\avr@instr@stepn{1}%
|
||||
\avr@test@REG{r30}{11111101}
|
||||
\avr@test@SREG{00000100}
|
||||
}
|
||||
\preto\avr@test{\avr@test@SUBI}
|
||||
|
||||
%%% Local Variables:
|
||||
%%% mode: latex
|
||||
%%% TeX-master: "avr.tex"
|
||||
|
Loading…
Reference in New Issue
Block a user