mirror of
git://git.gnupg.org/gnupg.git
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* longlong.h: Replaced all K&R multiline strings by ISO ones for
the sake of modern compilers. Suggested by Marco Parrone.
This commit is contained in:
Werner Koch
parent
6b50533fe1
commit
9a4e2a4c86
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@ -1,3 +1,8 @@
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2002-07-24 Werner Koch <wk@gnupg.org>
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* longlong.h: Replaced all K&R multiline strings by ISO ones for
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the sake of modern compilers. Suggested by Marco Parrone.
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2002-05-10 Stefan Bellon <sbellon@sbellon.de>
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* mpiutil.c (mpi_alloc_like/mpi_debug_alloc_like): Added code
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452
mpi/longlong.h
452
mpi/longlong.h
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@ -2,7 +2,7 @@
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Note: I added some stuff for use with gnupg
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Copyright (C) 1991, 1992, 1993, 1994, 1996, 1998,
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2000, 2001 Free Software Foundation, Inc.
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2000, 2001, 2002 Free Software Foundation, Inc.
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This file is free software; you can redistribute it and/or modify
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it under the terms of the GNU Library General Public License as published by
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@ -115,8 +115,8 @@ MA 02111-1307, USA. */
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***************************************/
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#if (defined (__a29k__) || defined (_AM29K)) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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__asm__ ("add %1,%4,%5
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addc %0,%2,%3" \
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__asm__ ("add %1,%4,%5\n" \
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"addc %0,%2,%3" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "%r" ((USItype)(ah)), \
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@ -124,8 +124,8 @@ MA 02111-1307, USA. */
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"%r" ((USItype)(al)), \
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"rI" ((USItype)(bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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__asm__ ("sub %1,%4,%5
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subc %0,%2,%3" \
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__asm__ ("sub %1,%4,%5\n" \
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"subc %0,%2,%3" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "r" ((USItype)(ah)), \
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@ -186,8 +186,8 @@ extern UDItype __udiv_qrnnd ();
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***************************************/
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#if defined (__arm__) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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__asm__ ("adds %1, %4, %5
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adc %0, %2, %3" \
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__asm__ ("adds %1, %4, %5\n" \
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"adc %0, %2, %3" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "%r" ((USItype)(ah)), \
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@ -195,8 +195,8 @@ extern UDItype __udiv_qrnnd ();
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"%r" ((USItype)(al)), \
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"rI" ((USItype)(bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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__asm__ ("subs %1, %4, %5
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sbc %0, %2, %3" \
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__asm__ ("subs %1, %4, %5\n" \
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"sbc %0, %2, %3" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "r" ((USItype)(ah)), \
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@ -205,32 +205,32 @@ extern UDItype __udiv_qrnnd ();
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"rI" ((USItype)(bl)))
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#if defined __ARM_ARCH_2__ || defined __ARM_ARCH_3__
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#define umul_ppmm(xh, xl, a, b) \
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__asm__ ("%@ Inlined umul_ppmm
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mov %|r0, %2, lsr #16 @ AAAA
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mov %|r2, %3, lsr #16 @ BBBB
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bic %|r1, %2, %|r0, lsl #16 @ aaaa
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bic %0, %3, %|r2, lsl #16 @ bbbb
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mul %1, %|r1, %|r2 @ aaaa * BBBB
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mul %|r2, %|r0, %|r2 @ AAAA * BBBB
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mul %|r1, %0, %|r1 @ aaaa * bbbb
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mul %0, %|r0, %0 @ AAAA * bbbb
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adds %|r0, %1, %0 @ central sum
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addcs %|r2, %|r2, #65536
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adds %1, %|r1, %|r0, lsl #16
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adc %0, %|r2, %|r0, lsr #16" \
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__asm__ ("%@ Inlined umul_ppmm\n" \
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"mov %|r0, %2, lsr #16 @ AAAA\n" \
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"mov %|r2, %3, lsr #16 @ BBBB\n" \
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"bic %|r1, %2, %|r0, lsl #16 @ aaaa\n" \
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"bic %0, %3, %|r2, lsl #16 @ bbbb\n" \
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"mul %1, %|r1, %|r2 @ aaaa * BBBB\n" \
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"mul %|r2, %|r0, %|r2 @ AAAA * BBBB\n" \
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"mul %|r1, %0, %|r1 @ aaaa * bbbb\n" \
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"mul %0, %|r0, %0 @ AAAA * bbbb\n" \
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"adds %|r0, %1, %0 @ central sum\n" \
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"addcs %|r2, %|r2, #65536\n" \
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"adds %1, %|r1, %|r0, lsl #16\n" \
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"adc %0, %|r2, %|r0, lsr #16" \
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: "=&r" ((USItype)(xh)), \
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"=r" ((USItype)(xl)) \
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: "r" ((USItype)(a)), \
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"r" ((USItype)(b)) \
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: "r0", "r1", "r2")
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#else
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#define umul_ppmm(xh, xl, a, b) \
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__asm__ ("%@ Inlined umul_ppmm
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umull %r1, %r0, %r2, %r3" \
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: "=&r" ((USItype)(xh)), \
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"=r" ((USItype)(xl)) \
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: "r" ((USItype)(a)), \
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"r" ((USItype)(b)) \
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#define umul_ppmm(xh, xl, a, b) \
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__asm__ ("%@ Inlined umul_ppmm\n" \
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"umull %r1, %r0, %r2, %r3" \
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: "=&r" ((USItype)(xh)), \
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"=r" ((USItype)(xl)) \
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: "r" ((USItype)(a)), \
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"r" ((USItype)(b)) \
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: "r0", "r1")
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#endif
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#define UMUL_TIME 20
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@ -274,8 +274,8 @@ extern UDItype __udiv_qrnnd ();
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***************************************/
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#if defined (__gmicro__) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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__asm__ ("add.w %5,%1
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addx %3,%0" \
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__asm__ ("add.w %5,%1\n" \
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"addx %3,%0" \
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: "=g" ((USItype)(sh)), \
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"=&g" ((USItype)(sl)) \
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: "%0" ((USItype)(ah)), \
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@ -283,8 +283,8 @@ extern UDItype __udiv_qrnnd ();
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"%1" ((USItype)(al)), \
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"g" ((USItype)(bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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__asm__ ("sub.w %5,%1
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subx %3,%0" \
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__asm__ ("sub.w %5,%1\n" \
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"subx %3,%0" \
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: "=g" ((USItype)(sh)), \
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"=&g" ((USItype)(sl)) \
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: "0" ((USItype)(ah)), \
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@ -317,8 +317,8 @@ extern UDItype __udiv_qrnnd ();
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***************************************/
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#if defined (__hppa) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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__asm__ ("add %4,%5,%1
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addc %2,%3,%0" \
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__asm__ ("add %4,%5,%1\n" \
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"addc %2,%3,%0" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "%rM" ((USItype)(ah)), \
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@ -326,8 +326,8 @@ extern UDItype __udiv_qrnnd ();
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"%rM" ((USItype)(al)), \
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"rM" ((USItype)(bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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__asm__ ("sub %4,%5,%1
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subb %2,%3,%0" \
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__asm__ ("sub %4,%5,%1\n" \
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"subb %2,%3,%0" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "rM" ((USItype)(ah)), \
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@ -362,25 +362,25 @@ extern UDItype __udiv_qrnnd ();
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extern USItype __udiv_qrnnd ();
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#endif /* LONGLONG_STANDALONE */
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#define count_leading_zeros(count, x) \
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do { \
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USItype __tmp; \
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__asm__ ( \
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"ldi 1,%0
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extru,= %1,15,16,%%r0 ; Bits 31..16 zero?
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extru,tr %1,15,16,%1 ; No. Shift down, skip add.
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ldo 16(%0),%0 ; Yes. Perform add.
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extru,= %1,23,8,%%r0 ; Bits 15..8 zero?
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extru,tr %1,23,8,%1 ; No. Shift down, skip add.
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ldo 8(%0),%0 ; Yes. Perform add.
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extru,= %1,27,4,%%r0 ; Bits 7..4 zero?
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extru,tr %1,27,4,%1 ; No. Shift down, skip add.
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ldo 4(%0),%0 ; Yes. Perform add.
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extru,= %1,29,2,%%r0 ; Bits 3..2 zero?
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extru,tr %1,29,2,%1 ; No. Shift down, skip add.
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ldo 2(%0),%0 ; Yes. Perform add.
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extru %1,30,1,%1 ; Extract bit 1.
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sub %0,%1,%0 ; Subtract it.
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" : "=r" (count), "=r" (__tmp) : "1" (x)); \
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do { \
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USItype __tmp; \
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__asm__ ( \
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"ldi 1,%0 \n" \
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"extru,= %1,15,16,%%r0 ; Bits 31..16 zero? \n" \
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"extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n" \
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"ldo 16(%0),%0 ; Yes. Perform add. \n" \
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"extru,= %1,23,8,%%r0 ; Bits 15..8 zero? \n" \
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"extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n" \
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"ldo 8(%0),%0 ; Yes. Perform add. \n" \
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"extru,= %1,27,4,%%r0 ; Bits 7..4 zero? \n" \
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"extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n" \
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"ldo 4(%0),%0 ; Yes. Perform add. \n" \
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"extru,= %1,29,2,%%r0 ; Bits 3..2 zero? \n" \
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"extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n" \
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"ldo 2(%0),%0 ; Yes. Perform add. \n" \
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"extru %1,30,1,%1 ; Extract bit 1. \n" \
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"sub %0,%1,%0 ; Subtract it. " \
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: "=r" (count), "=r" (__tmp) : "1" (x)); \
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} while (0)
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#endif /* hppa */
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@ -435,8 +435,8 @@ extern USItype __udiv_qrnnd ();
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***************************************/
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#if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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__asm__ ("addl %5,%1
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adcl %3,%0" \
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__asm__ ("addl %5,%1\n" \
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"adcl %3,%0" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "%0" ((USItype)(ah)), \
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@ -444,8 +444,8 @@ extern USItype __udiv_qrnnd ();
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"%1" ((USItype)(al)), \
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"g" ((USItype)(bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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__asm__ ("subl %5,%1
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sbbl %3,%0" \
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__asm__ ("subl %5,%1\n" \
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"sbbl %3,%0" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "0" ((USItype)(ah)), \
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@ -488,7 +488,8 @@ extern USItype __udiv_qrnnd ();
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***************************************/
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#if defined (__i860__) && W_TYPE_SIZE == 32
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#define rshift_rhlc(r,h,l,c) \
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__asm__ ("shr %3,r0,r0\;shrd %1,%2,%0" \
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__asm__ ("shr %3,r0,r0\n" \
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"shrd %1,%2,%0" \
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"=r" (r) : "r" (h), "r" (l), "rn" (c))
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#endif /* i860 */
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@ -497,7 +498,9 @@ extern USItype __udiv_qrnnd ();
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***************************************/
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#if defined (__i960__) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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__asm__ ("cmpo 1,0\;addc %5,%4,%1\;addc %3,%2,%0" \
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__asm__ ("cmpo 1,0\n" \
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"addc %5,%4,%1\n" \
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"addc %3,%2,%0" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "%dI" ((USItype)(ah)), \
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@ -505,7 +508,9 @@ extern USItype __udiv_qrnnd ();
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"%dI" ((USItype)(al)), \
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"dI" ((USItype)(bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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__asm__ ("cmpo 0,0\;subc %5,%4,%1\;subc %3,%2,%0" \
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__asm__ ("cmpo 0,0\n" \
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"subc %5,%4,%1\n" \
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"subc %3,%2,%0" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "dI" ((USItype)(ah)), \
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@ -568,8 +573,8 @@ extern USItype __udiv_qrnnd ();
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***************************************/
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#if (defined (__mc68000__) || defined (__mc68020__) || defined (__NeXT__) || defined(mc68020)) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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__asm__ ("add%.l %5,%1
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addx%.l %3,%0" \
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__asm__ ("add%.l %5,%1\n" \
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"addx%.l %3,%0" \
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: "=d" ((USItype)(sh)), \
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"=&d" ((USItype)(sl)) \
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: "%0" ((USItype)(ah)), \
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@ -577,8 +582,8 @@ extern USItype __udiv_qrnnd ();
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"%1" ((USItype)(al)), \
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"g" ((USItype)(bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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__asm__ ("sub%.l %5,%1
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subx%.l %3,%0" \
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__asm__ ("sub%.l %5,%1\n" \
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"subx%.l %3,%0" \
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: "=d" ((USItype)(sh)), \
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"=&d" ((USItype)(sl)) \
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: "0" ((USItype)(ah)), \
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@ -615,32 +620,32 @@ extern USItype __udiv_qrnnd ();
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#define COUNT_LEADING_ZEROS_0 32
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#else /* not mc68020 */
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#define umul_ppmm(xh, xl, a, b) \
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do { USItype __umul_tmp1, __umul_tmp2; \
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__asm__ ("| Inlined umul_ppmm
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move%.l %5,%3
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move%.l %2,%0
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move%.w %3,%1
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swap %3
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swap %0
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mulu %2,%1
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mulu %3,%0
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mulu %2,%3
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swap %2
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mulu %5,%2
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add%.l %3,%2
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jcc 1f
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add%.l %#0x10000,%0
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1: move%.l %2,%3
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clr%.w %2
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swap %2
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swap %3
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clr%.w %3
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add%.l %3,%1
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addx%.l %2,%0
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| End inlined umul_ppmm" \
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: "=&d" ((USItype)(xh)), "=&d" ((USItype)(xl)), \
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"=d" (__umul_tmp1), "=&d" (__umul_tmp2) \
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: "%2" ((USItype)(a)), "d" ((USItype)(b))); \
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do { USItype __umul_tmp1, __umul_tmp2; \
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__asm__ ("| Inlined umul_ppmm \n" \
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" move%.l %5,%3 \n" \
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" move%.l %2,%0 \n" \
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" move%.w %3,%1 \n" \
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" swap %3 \n" \
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" swap %0 \n" \
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" mulu %2,%1 \n" \
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" mulu %3,%0 \n" \
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" mulu %2,%3 \n" \
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" swap %2 \n" \
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" mulu %5,%2 \n" \
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" add%.l %3,%2 \n" \
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" jcc 1f \n" \
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" add%.l %#0x10000,%0 \n" \
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"1: move%.l %2,%3 \n" \
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" clr%.w %2 \n" \
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" swap %2 \n" \
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" swap %3 \n" \
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" clr%.w %3 \n" \
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" add%.l %3,%1 \n" \
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" addx%.l %2,%0 \n" \
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" | End inlined umul_ppmm" \
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: "=&d" ((USItype)(xh)), "=&d" ((USItype)(xl)), \
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"=d" (__umul_tmp1), "=&d" (__umul_tmp2) \
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: "%2" ((USItype)(a)), "d" ((USItype)(b))); \
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} while (0)
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#define UMUL_TIME 100
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#define UDIV_TIME 400
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|
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@ -653,8 +658,8 @@ extern USItype __udiv_qrnnd ();
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***************************************/
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#if defined (__m88000__) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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||||
__asm__ ("addu.co %1,%r4,%r5
|
||||
addu.ci %0,%r2,%r3" \
|
||||
__asm__ ("addu.co %1,%r4,%r5\n" \
|
||||
"addu.ci %0,%r2,%r3" \
|
||||
: "=r" ((USItype)(sh)), \
|
||||
"=&r" ((USItype)(sl)) \
|
||||
: "%rJ" ((USItype)(ah)), \
|
||||
|
|
@ -662,8 +667,8 @@ extern USItype __udiv_qrnnd ();
|
|||
"%rJ" ((USItype)(al)), \
|
||||
"rJ" ((USItype)(bl)))
|
||||
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
|
||||
__asm__ ("subu.co %1,%r4,%r5
|
||||
subu.ci %0,%r2,%r3" \
|
||||
__asm__ ("subu.co %1,%r4,%r5\n" \
|
||||
"subu.ci %0,%r2,%r3" \
|
||||
: "=r" ((USItype)(sh)), \
|
||||
"=&r" ((USItype)(sl)) \
|
||||
: "rJ" ((USItype)(ah)), \
|
||||
|
|
@ -705,7 +710,6 @@ extern USItype __udiv_qrnnd ();
|
|||
#endif /* __m88110__ */
|
||||
#endif /* __m88000__ */
|
||||
|
||||
|
||||
/***************************************
|
||||
************** MIPS *****************
|
||||
***************************************/
|
||||
|
|
@ -719,9 +723,9 @@ extern USItype __udiv_qrnnd ();
|
|||
"d" ((USItype)(v)))
|
||||
#else
|
||||
#define umul_ppmm(w1, w0, u, v) \
|
||||
__asm__ ("multu %2,%3
|
||||
mflo %0
|
||||
mfhi %1" \
|
||||
__asm__ ("multu %2,%3 \n" \
|
||||
"mflo %0 \n" \
|
||||
"mfhi %1" \
|
||||
: "=d" ((USItype)(w0)), \
|
||||
"=d" ((USItype)(w1)) \
|
||||
: "d" ((USItype)(u)), \
|
||||
|
|
@ -744,9 +748,9 @@ extern USItype __udiv_qrnnd ();
|
|||
"d" ((UDItype)(v)))
|
||||
#else
|
||||
#define umul_ppmm(w1, w0, u, v) \
|
||||
__asm__ ("dmultu %2,%3
|
||||
mflo %0
|
||||
mfhi %1" \
|
||||
__asm__ ("dmultu %2,%3 \n" \
|
||||
"mflo %0 \n" \
|
||||
"mfhi %1" \
|
||||
: "=d" ((UDItype)(w0)), \
|
||||
"=d" ((UDItype)(w1)) \
|
||||
: "d" ((UDItype)(u)), \
|
||||
|
|
@ -926,8 +930,8 @@ extern USItype __udiv_qrnnd ();
|
|||
***************************************/
|
||||
#if defined (__pyr__) && W_TYPE_SIZE == 32
|
||||
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
|
||||
__asm__ ("addw %5,%1
|
||||
addwc %3,%0" \
|
||||
__asm__ ("addw %5,%1 \n" \
|
||||
"addwc %3,%0" \
|
||||
: "=r" ((USItype)(sh)), \
|
||||
"=&r" ((USItype)(sl)) \
|
||||
: "%0" ((USItype)(ah)), \
|
||||
|
|
@ -935,8 +939,8 @@ extern USItype __udiv_qrnnd ();
|
|||
"%1" ((USItype)(al)), \
|
||||
"g" ((USItype)(bl)))
|
||||
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
|
||||
__asm__ ("subw %5,%1
|
||||
subwb %3,%0" \
|
||||
__asm__ ("subw %5,%1 \n" \
|
||||
"subwb %3,%0" \
|
||||
: "=r" ((USItype)(sh)), \
|
||||
"=&r" ((USItype)(sl)) \
|
||||
: "0" ((USItype)(ah)), \
|
||||
|
|
@ -948,8 +952,8 @@ extern USItype __udiv_qrnnd ();
|
|||
({union {UDItype __ll; \
|
||||
struct {USItype __h, __l;} __i; \
|
||||
} __xx; \
|
||||
__asm__ ("movw %1,%R0
|
||||
uemul %2,%0" \
|
||||
__asm__ ("movw %1,%R0 \n" \
|
||||
"uemul %2,%0" \
|
||||
: "=&r" (__xx.__ll) \
|
||||
: "g" ((USItype) (u)), \
|
||||
"g" ((USItype)(v))); \
|
||||
|
|
@ -962,8 +966,8 @@ extern USItype __udiv_qrnnd ();
|
|||
***************************************/
|
||||
#if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
|
||||
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
|
||||
__asm__ ("a %1,%5
|
||||
ae %0,%3" \
|
||||
__asm__ ("a %1,%5 \n" \
|
||||
"ae %0,%3" \
|
||||
: "=r" ((USItype)(sh)), \
|
||||
"=&r" ((USItype)(sl)) \
|
||||
: "%0" ((USItype)(ah)), \
|
||||
|
|
@ -971,8 +975,8 @@ extern USItype __udiv_qrnnd ();
|
|||
"%1" ((USItype)(al)), \
|
||||
"r" ((USItype)(bl)))
|
||||
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
|
||||
__asm__ ("s %1,%5
|
||||
se %0,%3" \
|
||||
__asm__ ("s %1,%5\n" \
|
||||
"se %0,%3" \
|
||||
: "=r" ((USItype)(sh)), \
|
||||
"=&r" ((USItype)(sl)) \
|
||||
: "0" ((USItype)(ah)), \
|
||||
|
|
@ -983,26 +987,26 @@ extern USItype __udiv_qrnnd ();
|
|||
do { \
|
||||
USItype __m0 = (m0), __m1 = (m1); \
|
||||
__asm__ ( \
|
||||
"s r2,r2
|
||||
mts r10,%2
|
||||
m r2,%3
|
||||
m r2,%3
|
||||
m r2,%3
|
||||
m r2,%3
|
||||
m r2,%3
|
||||
m r2,%3
|
||||
m r2,%3
|
||||
m r2,%3
|
||||
m r2,%3
|
||||
m r2,%3
|
||||
m r2,%3
|
||||
m r2,%3
|
||||
m r2,%3
|
||||
m r2,%3
|
||||
m r2,%3
|
||||
m r2,%3
|
||||
cas %0,r2,r0
|
||||
mfs r10,%1" \
|
||||
"s r2,r2 \n" \
|
||||
"mts r10,%2 \n" \
|
||||
"m r2,%3 \n" \
|
||||
"m r2,%3 \n" \
|
||||
"m r2,%3 \n" \
|
||||
"m r2,%3 \n" \
|
||||
"m r2,%3 \n" \
|
||||
"m r2,%3 \n" \
|
||||
"m r2,%3 \n" \
|
||||
"m r2,%3 \n" \
|
||||
"m r2,%3 \n" \
|
||||
"m r2,%3 \n" \
|
||||
"m r2,%3 \n" \
|
||||
"m r2,%3 \n" \
|
||||
"m r2,%3 \n" \
|
||||
"m r2,%3 \n" \
|
||||
"m r2,%3 \n" \
|
||||
"m r2,%3 \n" \
|
||||
"cas %0,r2,r0 \n" \
|
||||
"mfs r10,%1" \
|
||||
: "=r" ((USItype)(ph)), \
|
||||
"=r" ((USItype)(pl)) \
|
||||
: "%r" (__m0), \
|
||||
|
|
@ -1036,9 +1040,9 @@ extern USItype __udiv_qrnnd ();
|
|||
#if defined (__sh2__) && W_TYPE_SIZE == 32
|
||||
#define umul_ppmm(w1, w0, u, v) \
|
||||
__asm__ ( \
|
||||
"dmulu.l %2,%3
|
||||
sts macl,%1
|
||||
sts mach,%0" \
|
||||
"dmulu.l %2,%3\n" \
|
||||
"sts macl,%1\n" \
|
||||
"sts mach,%0" \
|
||||
: "=r" ((USItype)(w1)), \
|
||||
"=r" ((USItype)(w0)) \
|
||||
: "r" ((USItype)(u)), \
|
||||
|
|
@ -1052,8 +1056,8 @@ extern USItype __udiv_qrnnd ();
|
|||
***************************************/
|
||||
#if defined (__sparc__) && W_TYPE_SIZE == 32
|
||||
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
|
||||
__asm__ ("addcc %r4,%5,%1
|
||||
addx %r2,%3,%0" \
|
||||
__asm__ ("addcc %r4,%5,%1\n" \
|
||||
"addx %r2,%3,%0" \
|
||||
: "=r" ((USItype)(sh)), \
|
||||
"=&r" ((USItype)(sl)) \
|
||||
: "%rJ" ((USItype)(ah)), \
|
||||
|
|
@ -1062,8 +1066,8 @@ extern USItype __udiv_qrnnd ();
|
|||
"rI" ((USItype)(bl)) \
|
||||
__CLOBBER_CC)
|
||||
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
|
||||
__asm__ ("subcc %r4,%5,%1
|
||||
subx %r2,%3,%0" \
|
||||
__asm__ ("subcc %r4,%5,%1\n" \
|
||||
"subx %r2,%3,%0" \
|
||||
: "=r" ((USItype)(sh)), \
|
||||
"=&r" ((USItype)(sl)) \
|
||||
: "rJ" ((USItype)(ah)), \
|
||||
|
|
@ -1109,45 +1113,45 @@ extern USItype __udiv_qrnnd ();
|
|||
"r" ((USItype)(v)))
|
||||
#define UMUL_TIME 5
|
||||
#define udiv_qrnnd(q, r, n1, n0, d) \
|
||||
__asm__ ("! Inlined udiv_qrnnd
|
||||
wr %%g0,%2,%%y ! Not a delayed write for sparclite
|
||||
tst %%g0
|
||||
divscc %3,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%%g1
|
||||
divscc %%g1,%4,%0
|
||||
rd %%y,%1
|
||||
bl,a 1f
|
||||
add %1,%4,%1
|
||||
1: ! End of inline udiv_qrnnd" \
|
||||
__asm__ ("! Inlined udiv_qrnnd \n" \
|
||||
" wr %%g0,%2,%%y ! Not a delayed write for sparclite \n" \
|
||||
" tst %%g0 \n" \
|
||||
" divscc %3,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%%g1 \n" \
|
||||
" divscc %%g1,%4,%0 \n" \
|
||||
" rd %%y,%1 \n" \
|
||||
" bl,a 1f \n" \
|
||||
" add %1,%4,%1 \n" \
|
||||
"1: ! End of inline udiv_qrnnd" \
|
||||
: "=r" ((USItype)(q)), \
|
||||
"=r" ((USItype)(r)) \
|
||||
: "r" ((USItype)(n1)), \
|
||||
|
|
@ -1167,46 +1171,46 @@ extern USItype __udiv_qrnnd ();
|
|||
/* Default to sparc v7 versions of umul_ppmm and udiv_qrnnd. */
|
||||
#ifndef umul_ppmm
|
||||
#define umul_ppmm(w1, w0, u, v) \
|
||||
__asm__ ("! Inlined umul_ppmm
|
||||
wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr
|
||||
sra %3,31,%%g2 ! Don't move this insn
|
||||
and %2,%%g2,%%g2 ! Don't move this insn
|
||||
andcc %%g0,0,%%g1 ! Don't move this insn
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,%3,%%g1
|
||||
mulscc %%g1,0,%%g1
|
||||
add %%g1,%%g2,%0
|
||||
rd %%y,%1" \
|
||||
__asm__ ("! Inlined umul_ppmm \n" \
|
||||
" wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr \n" \
|
||||
" sra %3,31,%%g2 ! Don't move this insn \n" \
|
||||
" and %2,%%g2,%%g2 ! Don't move this insn \n" \
|
||||
" andcc %%g0,0,%%g1 ! Don't move this insn \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,%3,%%g1 \n" \
|
||||
" mulscc %%g1,0,%%g1 \n" \
|
||||
" add %%g1,%%g2,%0 \n" \
|
||||
" rd %%y,%1" \
|
||||
: "=r" ((USItype)(w1)), \
|
||||
"=r" ((USItype)(w0)) \
|
||||
: "%rI" ((USItype)(u)), \
|
||||
|
|
@ -1233,8 +1237,8 @@ extern USItype __udiv_qrnnd ();
|
|||
***************************************/
|
||||
#if defined (__vax__) && W_TYPE_SIZE == 32
|
||||
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
|
||||
__asm__ ("addl2 %5,%1
|
||||
adwc %3,%0" \
|
||||
__asm__ ("addl2 %5,%1\n" \
|
||||
"adwc %3,%0" \
|
||||
: "=g" ((USItype)(sh)), \
|
||||
"=&g" ((USItype)(sl)) \
|
||||
: "%0" ((USItype)(ah)), \
|
||||
|
|
@ -1242,8 +1246,8 @@ extern USItype __udiv_qrnnd ();
|
|||
"%1" ((USItype)(al)), \
|
||||
"g" ((USItype)(bl)))
|
||||
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
|
||||
__asm__ ("subl2 %5,%1
|
||||
sbwc %3,%0" \
|
||||
__asm__ ("subl2 %5,%1\n" \
|
||||
"sbwc %3,%0" \
|
||||
: "=g" ((USItype)(sh)), \
|
||||
"=&g" ((USItype)(sl)) \
|
||||
: "0" ((USItype)(ah)), \
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user