From 6fd2fb7209eeaf01c296fb66c99718b9ae424d67 Mon Sep 17 00:00:00 2001 From: Luis MartinGarcia Date: Fri, 24 Mar 2017 21:30:45 +0000 Subject: [PATCH] Fix incorrect ordering of SRC and DST MAC addresses in Ethernet and dot1q. This was reported by Derek Andrew. Thanks, Derek! --- specs.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/specs.py b/specs.py index 0da6602..0bdfc5e 100644 --- a/specs.py +++ b/specs.py @@ -65,7 +65,7 @@ # + Payload + # | | # +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ -ethernet="Source Address:48,Destination Address:48,EtherType:16,Payload:128?bits=48" +ethernet="Destination Address:48,Source Address:48,EtherType:16,Payload:128?bits=48" # +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ @@ -79,7 +79,7 @@ ethernet="Source Address:48,Destination Address:48,EtherType:16,Payload:128?bits # + Payload + # | | # +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ -dot1q="Source Address:48,Destination Address:48,TPID (0x8100):16,PCP:3,D:1,\ +dot1q="Destination Address:48,Source Address:48,TPID (0x8100):16,PCP:3,D:1,\ VLAN ID:12,EtherType:16,Payload:96?bits=48"