From b2e72cc133c3627d4a55889e30eba428e47d766b Mon Sep 17 00:00:00 2001 From: andres-mancera Date: Thu, 23 Apr 2015 07:45:39 -0700 Subject: [PATCH 1/2] Adding a few more files/file extensions/directories for Synopsys VCS. This new version adds: - fsdb waveforms - simv.db.dir/ directory for VHDL top configs - ucli.key - vc_hdrs.h - Also added a few comments about where each one of the files come from. --- Global/SynopsysVCS.gitignore | 58 ++++++++++++++++++++++++++++-------- 1 file changed, 46 insertions(+), 12 deletions(-) diff --git a/Global/SynopsysVCS.gitignore b/Global/SynopsysVCS.gitignore index 97317896..82ffb5be 100644 --- a/Global/SynopsysVCS.gitignore +++ b/Global/SynopsysVCS.gitignore @@ -1,23 +1,57 @@ -# Waveforms -*.vpd +########## Waveforms ####################################### +# Value Change Dumping (VCD) - IEEE Standard *.vcd +# VCDlus Dumping (VPD) - Synopsys proprietary format +*.vpd +# Extended VCD (EVCD) - Dump only port information *.evcd +# Fast Signal DataBase (FSDB) +*.fsdb -# Binary files + +########## Simulation executable file ###################### +# Default name of the simulation executable. A different +# name can be specified with this switch (the associated +# daidir database name is also taken from here) +# -o / simv -# Directories used for compilation -csrc/ -simv.daidir/ -# Log files +########## Intermediate files used for simulation ########## +# Generated for Verilog top configs +simv.daidir/ +# Generated for VHDL top configs +simv.db.dir/ +# Infrastructure necessary to co-simulate SystemC models +# with Verilog/VHDL models. An alternate directory may +# be specified with this switch: +# -Mdir= +csrc/ + + +########### Log files ###################################### +# The switch below allows to specify the file that will be +# used to write all messages from simulation +# -l *.log -# DVE, UCLI related files -DVEfiles/ -ucli* -*.key -# Coverage related files +########## Coverage-related files ########################## +# Generation of coverage result reports is done with urg +# and the database location is specified with this switch: +# urg -dir .vdb simv.vdb/ urgReport/ + + +########## DVE, UCLI related files ######################### +# DVE produces some logs that are created in this directory. +DVEfiles/ +ucli.key + + +########## C Language interface ############################ +# When the design is elaborated for DirectC, VCS will create +# a file in the current directory with declarations for +# C/C++ functions. +vc_hdrs.h From 4457dcc517a1da5dbdecc80a228b6814cab6c3d5 Mon Sep 17 00:00:00 2001 From: andres-mancera Date: Mon, 1 Jun 2015 14:38:55 -0700 Subject: [PATCH 2/2] Cleaning-up some of the comments that had been previously added. --- Global/SynopsysVCS.gitignore | 53 +++++++++++------------------------- 1 file changed, 16 insertions(+), 37 deletions(-) diff --git a/Global/SynopsysVCS.gitignore b/Global/SynopsysVCS.gitignore index 82ffb5be..eed2432f 100644 --- a/Global/SynopsysVCS.gitignore +++ b/Global/SynopsysVCS.gitignore @@ -1,57 +1,36 @@ -########## Waveforms ####################################### -# Value Change Dumping (VCD) - IEEE Standard +# Waveform formats *.vcd -# VCDlus Dumping (VPD) - Synopsys proprietary format *.vpd -# Extended VCD (EVCD) - Dump only port information *.evcd -# Fast Signal DataBase (FSDB) *.fsdb - -########## Simulation executable file ###################### -# Default name of the simulation executable. A different -# name can be specified with this switch (the associated -# daidir database name is also taken from here) -# -o / +# Default name of the simulation executable. A different name can be +# specified with this switch (the associated daidir database name is +# also taken from here): -o / simv - -########## Intermediate files used for simulation ########## -# Generated for Verilog top configs +# Generated for Verilog and VHDL top configs simv.daidir/ -# Generated for VHDL top configs simv.db.dir/ -# Infrastructure necessary to co-simulate SystemC models -# with Verilog/VHDL models. An alternate directory may -# be specified with this switch: -# -Mdir= + +# Infrastructure necessary to co-simulate SystemC models with +# Verilog/VHDL models. An alternate directory may be specified with this +# switch: -Mdir= csrc/ - -########### Log files ###################################### -# The switch below allows to specify the file that will be -# used to write all messages from simulation -# -l +# Log file - the following switch allows to specify the file that will be +# used to write all messages from simulation: -l *.log - -########## Coverage-related files ########################## -# Generation of coverage result reports is done with urg -# and the database location is specified with this switch: -# urg -dir .vdb +# Coverage results (generated with urg) and database location. The +# following switch can also be used: urg -dir .vdb simv.vdb/ urgReport/ - -########## DVE, UCLI related files ######################### -# DVE produces some logs that are created in this directory. +# DVE and UCLI related files. DVEfiles/ ucli.key - -########## C Language interface ############################ -# When the design is elaborated for DirectC, VCS will create -# a file in the current directory with declarations for -# C/C++ functions. +# When the design is elaborated for DirectC, the following file is created +# with declarations for C/C++ functions. vc_hdrs.h