705 lines
21 KiB
TeX
705 lines
21 KiB
TeX
\def\avr@debug#1{%
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\typeout{\the\avr@pc: #1}%
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}
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\def\avr@error#1{%
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\typeout{#1}\bye%
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}
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% Execution Engine
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\def\avr@instr@step{%
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\avr@code@get{\avr@instr@current}%
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%\avr@debug{\avr@instr@current}%
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% Dispatch Instruction by prefix
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\expandafter\avr@instr@dispatch\avr@instr@current\@nnil%
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\relax%
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}
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\newcount\avr@instr@steps
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\def\avr@instr@stepn#1{%
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\avr@instr@steps=#1%
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\def\avr@instr@stepn@helper{
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\ifnum \avr@instr@steps > 0%
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\advance \avr@instr@steps by -1\relax%
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\avr@instr@step%
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\avr@instr@stepn@helper%
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\fi%
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}%
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\avr@instr@stepn@helper%
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}
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\def\avr@instr@dispatch#1#2#3#4#5#6#7#8#9\@nnil{%
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\ifcsdef{avr@instr@#1#2#3#4#5#6#7#8#9}{%
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\csuse{avr@instr@#1#2#3#4#5#6#7#8#9}\@nnil%
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}{\ifcsdef{avr@instr@#1#2#3#4#5#6#7#8}{%
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\csuse{avr@instr@#1#2#3#4#5#6#7#8}#9\@nnil%
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}{\ifcsdef{avr@instr@#1#2#3#4#5#6#7}{%
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\csuse{avr@instr@#1#2#3#4#5#6#7}#8#9\@nnil%
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}{\ifcsdef{avr@instr@#1#2#3#4#5#6}{%
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\csuse{avr@instr@#1#2#3#4#5#6}#7#8#9\@nnil%
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}{\ifcsdef{avr@instr@#1#2#3#4#5}{%
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\csuse{avr@instr@#1#2#3#4#5}#6#7#8#9\@nnil%
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}{\ifcsdef{avr@instr@#1#2#3#4}{%
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\csuse{avr@instr@#1#2#3#4}#5#6#7#8#9\@nnil%
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}{\ifcsdef{avr@instr@#1#2#3}{%
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\csuse{avr@instr@#1#2#3}#4#5#6#7#8#9\@nnil%
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}{\ifcsdef{avr@instr@#1#2}{%
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\csuse{avr@instr@#1#2}#3#4#5#6#7#8#9\@nnil%
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}{\ifcsdef{avr@instr@#1}{%
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\csuse{avr@instr@#1}#2#3#4#5#6#7#8#9\@nnil%
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}{% Not found
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\avr@error{Unkown Instruction: #1#2#3#4#5#6#7#8#9}%
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}}}}}}}}}%
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}
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\def\avr@instr@matchend#1#2#3#4#5#6#7#8#9\@nnil{%
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\ifcsdef{avr@instr@#1:#2#3#4#5#6#7#8#9}{%
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\csuse{avr@instr@#1:#2#3#4#5#6#7#8#9}\@nnil%
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}{\ifcsdef{avr@instr@#1:#3#4#5#6#7#8#9}{%
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\csuse{avr@instr@#1:#3#4#5#6#7#8#9}#2\@nnil%
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}{\ifcsdef{avr@instr@#1:#4#5#6#7#8#9}{%
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\csuse{avr@instr@#1:#4#5#6#7#8#9}#2#3\@nnil%
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}{\ifcsdef{avr@instr@#1:#5#6#7#8#9}{%
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\csuse{avr@instr@#1:#5#6#7#8#9}#2#3#4\@nnil%
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}{\ifcsdef{avr@instr@#1:#6#7#8#9}{%
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\csuse{avr@instr@#1:#6#7#8#9}#2#3#4#5\@nnil%
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}{\ifcsdef{avr@instr@#1:#7#8#9}{%
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\csuse{avr@instr@#1:#7#8#9}#2#3#4#5#6\@nnil%
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}{\ifcsdef{avr@instr@#1:#9}{%
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\csuse{avr@instr@#1:#9}#2#3#4#5#6#7#8\@nnil%
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}{% Not found
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\avr@error{Unkown Instruction: #1:#2#3#4#5#6#7#8#9}%
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}}}}}}}%
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}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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% Match also from end for these prefixes
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\csdef{avr@instr@1001010}{\avr@instr@matchend{1001010}}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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% Helpers
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\def\avr@instr@gen@tworegs#1#2#3#4{%
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\avr@bin@msb@del{#3}{\avr@ADD@dddd}{\avr@ADD@d}%
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\avr@bin@msb@del{#4}{\avr@ADD@rrrr}{\avr@ADD@r}%
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\avr@code@set{#1\avr@ADD@r\avr@ADD@d\avr@ADD@dddd\avr@ADD@rrrr}{#2}%
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}
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\def\avr@instr@gen@regconst#1#2#3#4{%
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\avr@bin@msb@del{#3}{\avr@LDI@dddd}{\avr@LDI@d}%
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\avr@bin@nibble@high{#4}{\avr@LDI@H}%
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\avr@bin@nibble@low{#4}{\avr@LDI@L}%
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\avr@code@set{#1\avr@LDI@H\avr@LDI@dddd\avr@LDI@L}{#2}%
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}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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% Arithmetic instructions
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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% ADD -- Add without Carry
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\def\avr@instr@ADD{\avr@instr@gen@tworegs{000011}}
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\def\avr@instr@LSL#1#2{\avr@instr@gen@tworegs{000011}{#1}{#2}{#2}}
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\csdef{avr@instr@000011}#1#2#3#4#5#6#7\@nnil{%
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\def\avr@instr@extracarry{0}%
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\avr@reg@get{#1#7}{\avr@Rr}%
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\avr@reg@get{#2#3#4#5#6}{\avr@Rd}%
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\avr@debug{ADD - \%#2#3#4#5#6 <- #2#3#4#5#6 + \%#1#7}%
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\avr@debug{ADD - \avr@Rd <- \avr@Rd + \avr@Rr}%
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\def\avr@instr@adder@RrPreprocess{\avr@bit@id}%
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\csuse{avr@instr@adder@helper}%
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\avr@reg@set{\avr@Rx}{#2#3#4#5#6}%
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\avr@pc@inc%
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}
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% ADC -- Add with Carry
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\def\avr@instr@ADC{\avr@instr@gen@tworegs{000111}}
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\def\avr@instr@ROL#1#2{\avr@instr@ADC{#1}{#2}{#2}}
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\csdef{avr@instr@000111}#1#2#3#4#5#6#7\@nnil{%
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\avr@reg@get{#1#7}{\avr@Rr}%
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\avr@reg@get{#2#3#4#5#6}{\avr@Rd}%
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\avr@flag@get C \avr@instr@extracarry%
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\avr@debug{ADC - \%#2#3#4#5#6 <- #2#3#4#5#6 + \%#1#7}%
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\avr@debug{ADC - \avr@Rd <- \avr@Rd + \avr@Rr + \avr@instr@extracarry}%
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\def\avr@instr@adder@RrPreprocess{\avr@bit@id}%
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\csuse{avr@instr@adder@helper}%
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% Set the result register
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\avr@reg@set{\avr@Rx}{#2#3#4#5#6}%
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\avr@pc@inc%
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}
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% SUB -- Substract without carry
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\def\avr@instr@SUB{\avr@instr@gen@tworegs{000110}}
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\csdef{avr@instr@000110}#1#2#3#4#5#6#7\@nnil{%
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\avr@reg@get{#1#7}{\avr@Rr}%
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\avr@reg@get{#2#3#4#5#6}{\avr@Rd}%
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\def\avr@instr@extracarry{1}%
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\avr@debug{SUB - \%#2#3#4#5#6 <- #2#3#4#5#6 + \%#1#7}%
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\avr@debug{SUB - \avr@Rd <- \avr@Rd - \avr@Rr}%
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\def\avr@instr@adder@RrPreprocess{\avr@bit@negate}%
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\csuse{avr@instr@adder@helper}%
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% Set the result register
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\avr@reg@set{\avr@Rx}{#2#3#4#5#6}%
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\avr@pc@inc%
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}
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% SBC - Substract with Carry
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\def\avr@instr@SBC{\avr@instr@gen@tworegs{000010}}
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\csdef{avr@instr@000010}#1#2#3#4#5#6#7\@nnil{%
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\avr@reg@get{#1#7}{\avr@Rr}%
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\avr@reg@get{#2#3#4#5#6}{\avr@Rd}%
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\avr@flag@get C \@@carry%
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\xdef \avr@instr@extracarry {\avr@bit@negate \@@carry}%
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\avr@debug{SBC - \%#2#3#4#5#6 <- #2#3#4#5#6 + \%#1#7}%
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\avr@debug{SBC - \avr@Rd <- \avr@Rd - \avr@Rr - \@@carry}%
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\def\avr@instr@adder@RrPreprocess{\avr@bit@negate}%
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\csuse{avr@instr@adder@helper}%
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% Set the result register
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\avr@reg@set{\avr@Rx}{#2#3#4#5#6}%
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\avr@pc@inc%
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}
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% SUBI - Substract Immediate
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\def\avr@instr@SUBI{\avr@instr@gen@regconst{0101}}
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\csdef{avr@instr@0101}#1#2#3#4#5#6#7#8#9\@nnil{%
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\avr@reg@get{1#5#6#7#8}{\avr@Rd}%
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\def\avr@Rr{#1#2#3#4#9}%
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\def\avr@instr@extracarry{1}%
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\avr@debug{SUBI - \%#2#3#4#5#6 <- #2#3#4#5#6(=\avr@Rd) - \avr@Rr}%
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\def\avr@instr@adder@RrPreprocess{\avr@bit@negate}%
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\csuse{avr@instr@adder@helper}%
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% Set the result register
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\avr@reg@set{\avr@Rx}{1#5#6#7#8}%
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\avr@pc@inc%
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}
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% SBCI - Substract Immediate
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\def\avr@instr@SBCI{\avr@instr@gen@regconst{0100}}
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\csdef{avr@instr@0100}#1#2#3#4#5#6#7#8#9\@nnil{%
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\avr@reg@get{1#5#6#7#8}{\avr@Rd}%
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\def\avr@Rr{#1#2#3#4#9}%
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\avr@flag@get C \@@carry%
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\xdef \avr@instr@extracarry {\avr@bit@negate \@@carry}%
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\avr@debug{SBCI - \%#2#3#4#5#6 <- #2#3#4#5#6(=\avr@Rd) - \avr@Rr -\@@carry}%
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\def\avr@instr@adder@RrPreprocess{\avr@bit@negate}%
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\csuse{avr@instr@adder@helper}%
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% Set the result register
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\avr@reg@set{\avr@Rx}{1#5#6#7#8}%
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\avr@pc@inc%
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}
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% CP -- Compare without Carry
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\def\avr@instr@CP{\avr@instr@gen@tworegs{000101}}
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\csdef{avr@instr@000101}#1#2#3#4#5#6#7\@nnil{%
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\avr@reg@get{#1#7}{\avr@Rr}%
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\avr@reg@get{#2#3#4#5#6}{\avr@Rd}%
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\def\avr@instr@extracarry{1}%
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\avr@debug{CP - #2#3#4#5#6(=\avr@Rd) - \%#1#7(=\avr@Rr)}%
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\def\avr@instr@adder@RrPreprocess{\avr@bit@negate}%
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\csuse{avr@instr@adder@helper}%
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% Do not set the output register
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\avr@pc@inc%
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}
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% CPC -- Compare with Carry
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\def\avr@instr@CPC{\avr@instr@gen@tworegs{000001}}
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\csdef{avr@instr@000001}#1#2#3#4#5#6#7\@nnil{%
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\avr@reg@get{#1#7}{\avr@Rr}%
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\avr@reg@get{#2#3#4#5#6}{\avr@Rd}%
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\avr@flag@get C \@@carry%
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\xdef \avr@instr@extracarry {\avr@bit@negate \@@carry}%
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\avr@debug{CP - #2#3#4#5#6(=\avr@Rd) - \%#1#7(=\avr@Rr)}%
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\def\avr@instr@adder@RrPreprocess{\avr@bit@negate}%
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\csuse{avr@instr@adder@helper}%
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% Do not set the output register
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\avr@pc@inc%
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}
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% CPI - Compare Immediate
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\def\avr@instr@CPI{\avr@instr@gen@regconst{0011}}
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\csdef{avr@instr@0011}#1#2#3#4#5#6#7#8#9\@nnil{%
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\avr@reg@get{1#5#6#7#8}{\avr@Rd}%
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\def\avr@Rr{#1#2#3#4#9}%
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\avr@flag@get C \@@carry%
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\xdef \avr@instr@extracarry {\avr@bit@negate \@@carry}%
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\avr@debug{CPI - \%#2#3#4#5#6 <- #2#3#4#5#6(=\avr@Rd) - \avr@Rr -\@@carry}%
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\def\avr@instr@adder@RrPreprocess{\avr@bit@negate}%
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\csuse{avr@instr@adder@helper}%
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% Set the result register
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\avr@pc@inc%
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}
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\csdef{avr@instr@adder@helper}{%
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% Convert the Bitstring to Integer values
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\avr@bin@tocount{\avr@Rd}{\avr@accA}%
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\avr@bin@map{\avr@instr@adder@RrPreprocess}{\avr@Rr}{\avr@Rr}%
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\avr@bin@tocount{\avr@Rr}{\avr@accB}%
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\advance \avr@accA by \avr@accB\relax%
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\advance \avr@accA by \avr@instr@extracarry\relax%
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\avr@count@modulo@byte{\avr@accA}%
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\avr@count@tobin@b{\avr@accA}{\avr@Rx}%
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% Calculate the Flags
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\let\@@not=\avr@bit@negate%
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\let\@@and=\avr@bit@and%
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\let\@@or=\avr@bit@or%
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%% Carry
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\avr@bin@msb@get{\avr@Rr}{\@@R}%
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\avr@bin@msb@get{\avr@Rd}{\@@D}%
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\avr@bin@msb@get{\avr@Rx}{\@@X}%
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% \avr@debug{R: \@@R D: \@@D X:\@@X}%
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\def\avr@ADD@carry{%
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\@@or {\@@and \@@D {\@@not \@@X}}%
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{%
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\@@or{\@@and \@@R \@@D}%
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{\@@and \@@R {\@@not \@@X}}}}%
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\avr@flag@set C {\avr@instr@adder@RrPreprocess{\avr@ADD@carry}}%
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% Two's Complement Overflow
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\def\@@tmp{\@@or%
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{\@@and \@@D {\@@and \@@R {\@@not \@@X}}}%
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{\@@and {\@@not \@@D} {\@@and {\@@not \@@R} \@@X}}}%
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\avr@flag@set V \@@tmp%
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% Half Carry
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\avr@bin@getbit{\avr@Rr}{3}{\@@R}%
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\avr@bin@getbit{\avr@Rd}{3}{\@@D}%
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\avr@bin@getbit{\avr@Rx}{3}{\@@X}%
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\def\avr@ADD@carry{%
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\@@or {\@@and \@@D {\@@not \@@X}}%
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{%
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\@@or{\@@and \@@R \@@D}%
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{\@@and \@@R {\@@not \@@X}}}}%
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\avr@flag@set H {\avr@instr@adder@RrPreprocess{\avr@ADD@carry}}%
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%% Update Dependend Flags (N, Z, S)
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\avr@flags@update \avr@Rx%
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}
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% LDI -- Load Immediate Value
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\def\avr@instr@LDI{\avr@instr@gen@regconst{1110}}
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\def\avr@instr@SER#1#2{\avr@instr@gen@regconst{1110}{#1}{#2}{11111111}}
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\csdef{avr@instr@1110}#1#2#3#4#5#6#7#8#9\@nnil{%
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\avr@debug{LDI - \%1#5#6#7#8 <- #1#2#3#4#9}%
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\avr@reg@set{#1#2#3#4#9}{1#5#6#7#8}%
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\avr@pc@inc%
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}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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% Branch Instructions
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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% Encode 6 Bit Value to PC Offset
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\def\avr@instr@jump@enc#1#2{%
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\avr@count@tmpa=#1%
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\ifnum #1 < 0%
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\avr@count@tmpb=\avr@count@tmpa%
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\avr@count@tmpa=255%
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\advance \avr@count@tmpa by \avr@count@tmpb\relax%
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\advance \avr@count@tmpa by 1\relax%
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\fi%
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\avr@count@tobin@b{\avr@count@tmpa}{\@@res}%
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\avr@bin@msb@del{\@@res}{#2}{\@tempa}
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}
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\def\avr@instr@jump@dec#1#2{%
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\avr@bin@tocount{0#1}{\avr@count@tmpa}%
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\ifnum \avr@count@tmpa > 63%
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\avr@count@tmpb=\avr@count@tmpa%
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\avr@count@tmpa=-128%
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\advance \avr@count@tmpa by \avr@count@tmpb\relax%
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\fi%
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#2=\avr@count@tmpa\relax%
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}
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% BRBC -- Branch if Bit in SREG is cleared
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\def\avr@instr@BRBC#1#2#3{% ADD PC, Bit, Offset
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\avr@instr@jump@enc{#3}{\@@offset}%
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\avr@code@set{111101\@@offset#2}{#1}%
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}
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% BRBS -- Branch if Bit in SREG is set
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\def\avr@instr@BRBS#1#2#3{% ADD PC, Bit, Offset
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\avr@instr@jump@enc{#3}{\@@offset}%
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\avr@code@set{111100\@@offset#2}{#1}%
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}
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% BRCC - Branch if Carry Cleared
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\def\avr@instr@BRCC#1#2{% PC, Offset
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\avr@instr@BRBC{#1}{000}{#2}%
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}
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% BRSH - Branch if Same or Higher
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\def\avr@instr@BRSH{\avr@instr@BRCC}
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% BRCS - Branch if Carry Set
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\def\avr@instr@BRCS#1#2{% PC, Offset
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\avr@instr@BRBS{#1}{000}{#2}%
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}
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% BRSH - Branch if Lower
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\def\avr@instr@BRLO{\avr@instr@BRCS}
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% BRHC - Branch if Half Carry Cleared
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\def\avr@instr@BRHC#1#2{% PC, Offset
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\avr@instr@BRBC{#1}{101}{#2}%
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}
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% BRHS - Branch if Half Carry Set
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\def\avr@instr@BRHS#1#2{% PC, Offset
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\avr@instr@BRBS{#1}{101}{#2}%
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}
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% BRID - Branch if Global Interrupt Disabled
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\def\avr@instr@BRID#1#2{% PC, Offset
|
|
\avr@instr@BRBC{#1}{111}{#2}%
|
|
}
|
|
% BRIE - Branch if Global Interrupt Enabled
|
|
\def\avr@instr@BRIE#1#2{% PC, Offset
|
|
\avr@instr@BRBS{#1}{111}{#2}%
|
|
}
|
|
|
|
% BRMI - Branch if Minus
|
|
\def\avr@instr@BRMI#1#2{% PC, Offset
|
|
\avr@instr@BRBS{#1}{010}{#2}%
|
|
}
|
|
% BRPL - Branch if Plus
|
|
\def\avr@instr@BRPL#1#2{% PC, Offset
|
|
\avr@instr@BRBC{#1}{010}{#2}%
|
|
}
|
|
% BRNE - Branch if Not Equal
|
|
\def\avr@instr@BRNE#1#2{% PC, Offset
|
|
\avr@instr@BRBC{#1}{001}{#2}%
|
|
}
|
|
% BREQ - Branch if Equal
|
|
\def\avr@instr@BREQ#1#2{% PC, Offset
|
|
\avr@instr@BRBS{#1}{001}{#2}%
|
|
}
|
|
|
|
% BRTC - Branch if T flag cleared
|
|
\def\avr@instr@BRTC#1#2{% PC, Offset
|
|
\avr@instr@BRTC{#1}{110}{#2}%
|
|
}
|
|
% BRTS - Branch if T flag set
|
|
\def\avr@instr@BRTS#1#2{% PC, Offset
|
|
\avr@instr@BRTS{#1}{110}{#2}%
|
|
}
|
|
|
|
% BRVC - Branch if Overflow flag cleared
|
|
\def\avr@instr@BRVC#1#2{% PC, Offset
|
|
\avr@instr@BRBC{#1}{011}{#2}%
|
|
}
|
|
% BRVS - Branch if Overflow flag set
|
|
\def\avr@instr@BRVS#1#2{% PC, Offset
|
|
\avr@instr@BRBS{#1}{011}{#2}%
|
|
}
|
|
|
|
% BRGE - Branch if greater Equal (signed)
|
|
\def\avr@instr@BRGE#1#2{% PC, Offset
|
|
\avr@instr@BRBC{#1}{100}{#2}%
|
|
}
|
|
% BRLT - Branch if less than (signed)
|
|
\def\avr@instr@BRLT#1#2{% PC, Offset
|
|
\avr@instr@BRBS{#1}{100}{#2}%
|
|
}
|
|
|
|
% #1 = Value to be reached
|
|
\csdef{avr@instr@11110}#1#2#3#4#5#6#7#8#9\@nnil{
|
|
\edef\@@required{\avr@bit@negate #1}%
|
|
\def\@@offset{#2#3#4#5#6#7#8}%
|
|
\def\@@bit{00000#9}%
|
|
\avr@sreg@get{\@@sreg}%
|
|
\avr@bin@tocount{\@@bit}{\avr@count@tmpa}%
|
|
\edef\@@bit{\the\avr@count@tmpa}%
|
|
\avr@bin@getbit{\@@sreg}{\@@bit}{\@@found}%
|
|
\avr@count@tmpa=\@@required%
|
|
\avr@count@tmpb=\@@found\relax%
|
|
\avr@debug{BRB{CS} - (\@@sreg[\@@bit] == \@@required) ? +\@@offset : +0}
|
|
\ifnum \avr@count@tmpa = \avr@count@tmpb%
|
|
\avr@instr@jump@dec{\@@offset}{\avr@count@tmpa}%
|
|
\avr@debug{BRB -- JUMP \the\avr@count@tmpa}%
|
|
\avr@pc@add{\avr@count@tmpa}%
|
|
\fi%
|
|
\avr@pc@inc%
|
|
}
|
|
|
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
|
% Data transfert instructions
|
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
|
% MOV
|
|
\def\avr@instr@MOV{\avr@instr@gen@tworegs{001011}}
|
|
\csdef{avr@instr@001011}#1#2#3#4#5#6#7\@nnil{%
|
|
\avr@reg@get{#1#7}{\avr@Rr}%
|
|
\avr@reg@set{\avr@Rr}{#2#3#4#5#6}%
|
|
\avr@debug{MOV - #2#3#4#5#6 <- #1#7(=\avr@Rr)}
|
|
\avr@pc@inc%
|
|
}
|
|
|
|
% MOVW
|
|
\def\avr@instr@MOVW#1#2#3{%
|
|
\avr@bin@lsb@del{#2}{\avr@LDI@dddd}{\avr@LDI@d}%
|
|
\avr@bin@lsb@del{#3}{\avr@LDI@rrrr}{\avr@LDI@r}%
|
|
\avr@code@set{00000001\avr@LDI@dddd\avr@LDI@rrrr}{#1}%
|
|
}
|
|
\csdef{avr@instr@00000001}#1#2#3#4#5\@nnil{%
|
|
\avr@reg@get{#50}{\avr@Rr}%
|
|
\avr@reg@set{\avr@Rr}{#1#2#3#40}%
|
|
\avr@reg@get{#51}{\avr@Rd}%
|
|
\avr@reg@set{\avr@Rd}{#1#2#3#41}%
|
|
\avr@debug{MOV - #1#2#3#4[01] <- #5[01](=\avr@Rr:\avr@Rd)}
|
|
\avr@pc@inc%
|
|
}
|
|
|
|
|
|
|
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
|
% Misc
|
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
|
\def\avr@instr@BREAK#1{% BREAK PC
|
|
\avr@code@set{1001010110011000}{#1}%
|
|
}
|
|
|
|
\csdef{avr@instr@1001010110011000}\@nnil{%
|
|
\avr@debug{BREAK}%
|
|
\avr@instr@steps=0\relax%
|
|
\avr@pc@inc%
|
|
}
|
|
|
|
\def\avr@instr@NOP#1{%
|
|
\avr@code@set{0000000000000000}{#1}%
|
|
}
|
|
|
|
\csdef{avr@instr@0000000000000000}\@nnil{%
|
|
\avr@debug{NOP}%
|
|
\avr@pc@inc%
|
|
}
|
|
|
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
|
% Logical Instructions
|
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
|
\def\avr@instr@bitop@helper{%
|
|
\avr@debug{\avr@instr@bitop - {\avr@Rd} AND {\avr@Rr}}%
|
|
\csuse{avr@bin@\avr@instr@bitop}{\avr@Rr}{\avr@Rd}{\avr@Rx}%
|
|
\avr@flag@set V 0%
|
|
\avr@flags@update \avr@Rx%
|
|
}
|
|
|
|
\def\avr@instr@AND{\avr@instr@gen@tworegs{001000}}
|
|
\def\avr@instr@TST#1#2{\avr@instr@gen@tworegs{001000}{#1}{#2}{#2}}
|
|
\csdef{avr@instr@001000}#1#2#3#4#5#6#7\@nnil{%
|
|
\avr@reg@get{#1#7}{\avr@Rr}%
|
|
\avr@reg@get{#2#3#4#5#6}{\avr@Rd}%
|
|
\def\avr@instr@bitop{and}%
|
|
\avr@instr@bitop@helper%
|
|
% Set the result register
|
|
\avr@reg@set{\avr@Rx}{#2#3#4#5#6}%
|
|
\avr@pc@inc%
|
|
}
|
|
|
|
\def\avr@instr@ANDI{\avr@instr@gen@regconst{0111}}
|
|
\csdef{avr@instr@0111}#1#2#3#4#5#6#7#8#9\@nnil{%
|
|
\avr@reg@get{1#5#6#7#8}{\avr@Rd}%
|
|
\def\avr@Rr{#1#2#3#4#9}%
|
|
\def\avr@instr@bitop{and}%
|
|
\avr@instr@bitop@helper%
|
|
% Set the result register
|
|
\avr@reg@set{\avr@Rx}{1#5#6#7#8}%
|
|
\avr@pc@inc%
|
|
}
|
|
|
|
|
|
\def\avr@instr@OR{\avr@instr@gen@tworegs{001010}}
|
|
\csdef{avr@instr@001010}#1#2#3#4#5#6#7\@nnil{%
|
|
\avr@reg@get{#1#7}{\avr@Rr}%
|
|
\avr@reg@get{#2#3#4#5#6}{\avr@Rd}%
|
|
\def\avr@instr@bitop{or}%
|
|
\avr@instr@bitop@helper%
|
|
% Set the result register
|
|
\avr@reg@set{\avr@Rx}{#2#3#4#5#6}%
|
|
\avr@pc@inc%
|
|
}
|
|
|
|
\def\avr@instr@ORI{\avr@instr@gen@regconst{0110}}
|
|
\def\avr@instr@SBR{\avr@instr@ORI}
|
|
\csdef{avr@instr@0110}#1#2#3#4#5#6#7#8#9\@nnil{%
|
|
\avr@reg@get{1#5#6#7#8}{\avr@Rd}%
|
|
\def\avr@Rr{#1#2#3#4#9}%
|
|
\def\avr@instr@bitop{or}%
|
|
\avr@instr@bitop@helper%
|
|
% Set the result register
|
|
\avr@reg@set{\avr@Rx}{1#5#6#7#8}%
|
|
\avr@pc@inc%
|
|
}
|
|
|
|
\def\avr@instr@EOR{\avr@instr@gen@tworegs{001001}}
|
|
\def\avr@instr@CLR#1#2{\avr@instr@EOR{#1}{#2}{#2}}
|
|
\csdef{avr@instr@001001}#1#2#3#4#5#6#7\@nnil{%
|
|
\avr@reg@get{#1#7}{\avr@Rr}%
|
|
\avr@reg@get{#2#3#4#5#6}{\avr@Rd}%
|
|
\def\avr@instr@bitop{xor}%
|
|
\avr@instr@bitop@helper%
|
|
% Set the result register
|
|
\avr@reg@set{\avr@Rx}{#2#3#4#5#6}%
|
|
\avr@pc@inc%
|
|
}
|
|
|
|
\def\avr@instr@BSET#1#2{%
|
|
\avr@code@set{100101000#21000}{#1}%
|
|
}
|
|
\def\avr@instr@SEC#1{\avr@instr@BSET{#1}{000}}
|
|
\def\avr@instr@SEZ#1{\avr@instr@BSET{#1}{001}}
|
|
\def\avr@instr@SEN#1{\avr@instr@BSET{#1}{010}}
|
|
\def\avr@instr@SEV#1{\avr@instr@BSET{#1}{011}}
|
|
\def\avr@instr@SES#1{\avr@instr@BSET{#1}{100}}
|
|
\def\avr@instr@SEH#1{\avr@instr@BSET{#1}{101}}
|
|
\def\avr@instr@SET#1{\avr@instr@BSET{#1}{110}}
|
|
\def\avr@instr@SEI#1{\avr@instr@BSET{#1}{111}}
|
|
|
|
|
|
\def\avr@instr@BCLR#1#2{%
|
|
\avr@code@set{100101001#21000}{#1}%
|
|
}
|
|
\def\avr@instr@CLC#1{\avr@instr@BCLR{#1}{000}}
|
|
\def\avr@instr@CLZ#1{\avr@instr@BCLR{#1}{001}}
|
|
\def\avr@instr@CLN#1{\avr@instr@BCLR{#1}{010}}
|
|
\def\avr@instr@CLV#1{\avr@instr@BCLR{#1}{011}}
|
|
\def\avr@instr@CLS#1{\avr@instr@BCLR{#1}{100}}
|
|
\def\avr@instr@CLH#1{\avr@instr@BCLR{#1}{101}}
|
|
\def\avr@instr@CLT#1{\avr@instr@BCLR{#1}{110}}
|
|
\def\avr@instr@CLI#1{\avr@instr@BCLR{#1}{111}}
|
|
|
|
|
|
|
|
\def\avr@instr@BSET@helper#1#2{%
|
|
% BSET
|
|
\csdef{avr@instr@100101000#11000}\@nnil{%
|
|
\avr@debug{BSET #1 #2}%
|
|
\avr@flag@set #2 1%
|
|
\avr@pc@inc%
|
|
}%
|
|
\csdef{avr@instr@100101001#11000}\@nnil{%
|
|
\avr@debug{BCLR #2}%
|
|
\avr@flag@set #2 0%
|
|
\avr@pc@inc%
|
|
}\relax%
|
|
}
|
|
\avr@instr@BSET@helper{000}{C}
|
|
\avr@instr@BSET@helper{001}{Z}
|
|
\avr@instr@BSET@helper{010}{N}
|
|
\avr@instr@BSET@helper{011}{V}
|
|
\avr@instr@BSET@helper{100}{S}
|
|
\avr@instr@BSET@helper{101}{H}
|
|
\avr@instr@BSET@helper{110}{T}
|
|
\avr@instr@BSET@helper{111}{I}
|
|
|
|
\def\avr@instr@BST#1#2#3{\avr@code@set{1111101#20#3}{#1}}
|
|
\csdef{avr@instr@1111101}#1#2#3#4#5#6\@nnil{%
|
|
\avr@reg@get{#1#2#3#4#5}{\avr@Rd}%
|
|
\avr@bin@tocount{0000#6}{\avr@count@tmpa}%
|
|
\edef\@@X{\the\avr@count@tmpa}%
|
|
\avr@debug{BST T <- #1#2#3#4#5(=\avr@Rd):\@@X}%
|
|
\avr@bin@getbit{\avr@Rd}{\@@X}{\@@T}%
|
|
\avr@flag@set T \@@T%
|
|
\avr@pc@inc%
|
|
}
|
|
|
|
\def\avr@instr@BLD#1#2#3{\avr@code@set{1111100#20#3}{#1}}
|
|
\csdef{avr@instr@1111100}#1#2#3#4#5#6\@nnil{%
|
|
\avr@bin@tocount{0000#6}{\avr@count@tmpa}%
|
|
\avr@reg@get{#1#2#3#4#5}{\avr@Rd}%
|
|
\edef\@@X{\the\avr@count@tmpa}%
|
|
\avr@flag@get T \@@T%
|
|
\avr@debug{BLD #1#2#3#4#5(=\avr@Rd) |= \@@T<<\@@X}%
|
|
\avr@bin@setbit{\avr@Rd}{\@@X}{\@@T}{\avr@Rd}%
|
|
\avr@reg@set{\avr@Rd}{#1#2#3#4#5}%
|
|
\avr@pc@inc%
|
|
}
|
|
|
|
\def\avr@instr@NEG#1#2{\avr@code@set{1001010#20001}{#1}}
|
|
\csdef{avr@instr@1001010:0001}#1\@nnil{%
|
|
\avr@reg@get{#1}{\avr@Rr}%
|
|
\avr@debug{NEG: #1(=\avr@Rr)}%
|
|
\def\avr@Rd{00000000}%
|
|
\def\avr@instr@extracarry{1}%
|
|
\def\avr@instr@adder@RrPreprocess{\avr@bit@negate}%
|
|
\csuse{avr@instr@adder@helper}%
|
|
% Set the result register
|
|
\avr@reg@set{\avr@Rx}{#1}%
|
|
\avr@pc@inc%
|
|
}
|
|
|
|
\def\avr@instr@COM#1#2{\avr@code@set{1001010#20000}{#1}}
|
|
\csdef{avr@instr@1001010:0000}#1\@nnil{%
|
|
\avr@reg@get{#1}{\avr@Rr}%
|
|
\avr@debug{COM: #1(=\avr@Rr)}%
|
|
\avr@bin@negate{\avr@Rr}{\avr@Rx}%
|
|
\avr@flag@set C 1%
|
|
\avr@flag@set V 0%
|
|
\avr@flags@update \avr@Rx%
|
|
% Set the result register
|
|
\avr@reg@set{\avr@Rx}{#1}%
|
|
\avr@pc@inc%
|
|
}
|
|
|
|
% Skip if Bit in Register is Set (or not)
|
|
\def\avr@instr@SBRC#1#2#3{\avr@code@set{1111110#20#3}{#1}}
|
|
\def\avr@instr@SBRS#1#2#3{\avr@code@set{1111111#20#3}{#1}}
|
|
|
|
\csdef{avr@instr@111111}#1#2#3#4#5#6#7\@nnil{%
|
|
\def\@@required{#1}% 1 if if set
|
|
\avr@reg@get{#2#3#4#5#6}{\avr@Rr}%
|
|
\avr@bin@tocount{0000#7}{\avr@count@tmpa}%
|
|
\edef\@@bit{\the\avr@count@tmpa}%
|
|
\avr@bin@getbit{\avr@Rr}{\@@bit}{\@@found}%
|
|
\avr@debug{SBR[SC] Skip iff \avr@Rr:\@@bit(\@@found) == \@@required}%
|
|
\avr@count@tmpa=\@@found%
|
|
\avr@count@tmpb=\@@required\relax%
|
|
\ifnum \avr@count@tmpa = \avr@count@tmpb%
|
|
\avr@debug{SKIP one instruction}%
|
|
\avr@pc@inc%
|
|
\fi%
|
|
\avr@pc@inc%
|
|
}
|
|
|
|
\def\avr@instr@ASR#1#2{\avr@code@set{1001010#20101}{#1}}
|
|
\csdef{avr@instr@1001010:0101}#1\@nnil{%
|
|
\avr@reg@get{#1}{\avr@Rr}%
|
|
\avr@debug{ASR: #1(=\avr@Rr)}%
|
|
\avr@bin@shiftright@arith{\avr@Rr}{1}{\avr@Rx}{\@@carry}%
|
|
\avr@bin@msb@get{\avr@Rx}{\@@N}%
|
|
\avr@flag@set C \@@carry%
|
|
\avr@flag@set V {\avr@bit@xor \@@carry \@@N}%
|
|
\avr@flags@update \avr@Rx%
|
|
\avr@reg@set{\avr@Rx}{#1}%
|
|
\avr@pc@inc%
|
|
}
|
|
|
|
|
|
% LSL is implemented as ADD
|
|
\def\avr@instr@LSR#1#2{\avr@code@set{1001010#20110}{#1}}
|
|
\csdef{avr@instr@1001010:0110}#1\@nnil{%
|
|
\avr@reg@get{#1}{\avr@Rr}%
|
|
\avr@debug{LSL: #1(=\avr@Rr)}%
|
|
\avr@bin@shiftright{\avr@Rr}{1}{\avr@Rx}{\@@carry}%
|
|
\avr@bin@msb@get{\avr@Rx}{\@@N}%
|
|
\avr@flag@set C \@@carry%
|
|
\avr@flag@set V {\avr@bit@xor \@@carry \@@N}%
|
|
\avr@flags@update \avr@Rx%
|
|
\avr@reg@set{\avr@Rx}{#1}%
|
|
\avr@pc@inc%
|
|
}
|
|
|
|
% ROL is implemented as ADD
|
|
\def\avr@instr@ROR#1#2{\avr@code@set{1001010#20111}{#1}}
|
|
\csdef{avr@instr@1001010:0111}#1\@nnil{%
|
|
\avr@reg@get{#1}{\avr@Rr}%
|
|
\avr@flag@get C \@@carry%
|
|
\avr@debug{ROR: #1(=\@@carry:\avr@Rr)}%
|
|
\avr@bin@lsb@del{\@@carry\avr@Rr}{\avr@Rx}{\@@carry}%
|
|
\avr@bin@msb@get{\avr@Rx}{\@@N}%
|
|
\avr@flag@set C \@@carry%
|
|
\avr@flag@set V {\avr@bit@xor \@@carry \@@N}%
|
|
\avr@flags@update \avr@Rx%
|
|
\avr@reg@set{\avr@Rx}{#1}%
|
|
\avr@pc@inc%
|
|
}
|
|
|
|
%%% Local Variables:
|
|
%%% mode: latex
|
|
%%% TeX-master: "avr.tex"
|
|
%%% End:
|