344 lines
9.0 KiB
TeX
344 lines
9.0 KiB
TeX
%% Copyright (C) 2014 Christian Dietrich <stettberger@dokucode.de>
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%% -------------------------------------------------------
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%%
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%% This package may be distributed and/or modified under the conditions
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%% of the LaTeX Project Public License, either version 1.3c of this
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%% license or (at your option) any later version. The latest version of
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%% this license is in
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%%
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%% http://www.latex-project.org/lppl.txt
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%%
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%% and version 1.3c or later is part of all distributions of LaTeX
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%% version 2008/05/04 or later.
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%
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% The IO subsystem
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%
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%% Bootup
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\def\avr@init{%
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\avr@flag@init%
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\avr@reg@init%
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\avr@pc@init%
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\avr@stack@init%
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\avr@mem@init{1024}%
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\avr@io@init%
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\avr@instr@init%
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\avr@debug{Initialized AVR}%
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}
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\newcount\avr@accA
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\newcount\avr@accB
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\def\avr@dump@totex{%
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SREG:\avr@sreg@get{\@tempa}:='\@tempa' (ITHS VNZC)
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\ttfamily
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\begin{tabular}{llllllll}
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r0 :\avr@reg@get{00000}{\@tempa}:= '\@tempa' &
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r1 :\avr@reg@get{00001}{\@tempa}:= '\@tempa' &
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r2 :\avr@reg@get{00010}{\@tempa}:= '\@tempa' &
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r3 :\avr@reg@get{00011}{\@tempa}:= '\@tempa' \\
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r4 :\avr@reg@get{00100}{\@tempa}:= '\@tempa' &
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r5 :\avr@reg@get{00101}{\@tempa}:= '\@tempa' &
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r6 :\avr@reg@get{00110}{\@tempa}:= '\@tempa' &
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r7 :\avr@reg@get{00111}{\@tempa}:= '\@tempa' \\
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r8 :\avr@reg@get{01000}{\@tempa}:= '\@tempa' &
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r9 :\avr@reg@get{01001}{\@tempa}:= '\@tempa' &
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r10:\avr@reg@get{01010}{\@tempa}:= '\@tempa' &
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r11:\avr@reg@get{01011}{\@tempa}:= '\@tempa' \\
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r12:\avr@reg@get{01100}{\@tempa}:= '\@tempa' &
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r13:\avr@reg@get{01101}{\@tempa}:= '\@tempa' &
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r14:\avr@reg@get{01110}{\@tempa}:= '\@tempa' &
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r15:\avr@reg@get{01111}{\@tempa}:= '\@tempa' \\
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r16:\avr@reg@get{10000}{\@tempa}:= '\@tempa' &
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r17:\avr@reg@get{10001}{\@tempa}:= '\@tempa' &
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r18:\avr@reg@get{10010}{\@tempa}:= '\@tempa' &
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r19:\avr@reg@get{10011}{\@tempa}:= '\@tempa' \\
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r20:\avr@reg@get{10100}{\@tempa}:= '\@tempa' &
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r21:\avr@reg@get{10101}{\@tempa}:= '\@tempa' &
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r22:\avr@reg@get{10110}{\@tempa}:= '\@tempa' &
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r23:\avr@reg@get{10111}{\@tempa}:= '\@tempa' \\
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r24:\avr@reg@get{11000}{\@tempa}:= '\@tempa' &
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r25:\avr@reg@get{11001}{\@tempa}:= '\@tempa' &
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r26:\avr@reg@get{11010}{\@tempa}:= '\@tempa' &
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r27:\avr@reg@get{11011}{\@tempa}:= '\@tempa' \\
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r28:\avr@reg@get{11100}{\@tempa}:= '\@tempa' &
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r29:\avr@reg@get{11101}{\@tempa}:= '\@tempa' &
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r30:\avr@reg@get{11110}{\@tempa}:= '\@tempa' &
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r31:\avr@reg@get{11111}{\@tempa}:= '\@tempa' \\
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\end{tabular}
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}
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\def\avr@dump{%
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\avr@sreg@get{\@@X} \avr@debug{SREG::='\@@X' (ITHS VNZC)}
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\def\avr@dump@reg##1##2{%
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\avr@reg@get{\csuse{avr@##1}}{\@@X}%
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\avr@bin@tocount{\@@X}{\avr@count@tmpa}%
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\edef##2{##1=\the\avr@count@tmpa}%
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}%
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\def\avr@dump@row##1##2##3##4{%
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\avr@dump@reg{##1}{\@@A}%
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\avr@dump@reg{##2}{\@@B}%
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\avr@dump@reg{##3}{\@@C}%
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\avr@dump@reg{##4}{\@@D}%
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\avr@debug{(\@@A) (\@@B) (\@@C) (\@@D)}%
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}%
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\avr@dump@row{r0}{r1}{r2}{r3}%
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\avr@dump@row{r4}{r5}{r6}{r7}%
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\avr@dump@row{r8}{r9}{r10}{r11}%
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\avr@dump@row{r12}{r13}{r14}{r15}%
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\avr@dump@row{r16}{r17}{r18}{r19}%
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\avr@dump@row{r20}{r21}{r22}{r23}%
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\avr@dump@row{r24}{r25}{r26}{r27}%
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\avr@dump@row{r28}{r29}{r30}{r31}%
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}
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%% Status Register && Flags
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\def\avr@flag@set#1#2{% Register Name, Value \in 0,1
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\csxdef{avr@flag@#1}{#2}\relax%
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}
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\def\avr@flag@get#1#2{% Register Name, Target Macro
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\edef#2{\csuse{avr@flag@#1}}%
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}
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\def\avr@flag@init{%
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\avr@sreg@set{00000000}%
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}
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\def\avr@sreg@set#1{% Bitstring
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\def\avr@sreg@helper##1##2##3##4##5##6##7##8\@nnil{%
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\avr@flag@set{C}{##8} % Carry
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\avr@flag@set{Z}{##7} % Zero
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\avr@flag@set{N}{##6} % Negative
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\avr@flag@set{V}{##5} % Two's complement overflow indicator
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\avr@flag@set{S}{##4} % N \xor V, For Signed Tests
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\avr@flag@set{H}{##3} % Half Carry Flag
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\avr@flag@set{T}{##2} % Transfer bit
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\avr@flag@set{I}{##1} % Global Interrupt Enable
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}%
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\edef\@tempa{#1}%
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\expandafter \avr@sreg@helper \@tempa \@nnil%
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}
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\def\avr@sreg@get#1{% Target Macro
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\edef#1{%
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\csuse{avr@flag@I}%
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\csuse{avr@flag@T}%
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\csuse{avr@flag@H}%
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\csuse{avr@flag@S}%
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\csuse{avr@flag@V}%
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\csuse{avr@flag@N}%
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\csuse{avr@flag@Z}%
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\csuse{avr@flag@C}%
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}%
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}
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\def\avr@flags@update#1{%
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% Negate Flag
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\avr@bin@msb@get{#1}{\@@N}%
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\avr@flag@set N \@@N%
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% Zero Flag
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\avr@bin@tocount{#1}{\avr@count@tmpa}%
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\ifnum \avr@count@tmpa = 0%
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\avr@flag@set Z 1%
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\else%
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\avr@flag@set Z 0%
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\fi%
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% Signed Flag
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\avr@flag@get V \@@V%
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\edef\@@tmp{\avr@bit@xor \@@N \@@V}%
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\avr@flag@set S \@@tmp%
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}
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%% Registers
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\def\avr@reg@set#1#2{% Bitstring, Register Bitstring
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\csxdef{avr@reg@#2}{#1}%
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}
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\def\avr@reg@get#1#2{% Register Bitstring, Target Macro
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\edef#2{\csuse{avr@reg@#1}}%
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}
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\csdef{avr@X}{1101}
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\csdef{avr@Y}{1110}
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\csdef{avr@Z}{1111}
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\def\avr@regw@get#1#2{%
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\avr@reg@get{#11}{\@@high}%
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\avr@reg@get{#10}{\@@low}%
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\edef#2{\@@high \@@low}%
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}
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\def\avr@regw@set#1#2{%
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\edef\@@value{#1}%
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\avr@bin@word@low{\@@value}{\@@low}%
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\avr@bin@word@high{\@@value}{\@@high}%
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\avr@reg@set{\@@high}{#21}%
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\avr@reg@set{\@@low}{#20}%
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}
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\def\avr@reg@init{%
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\avr@reg@set{\avr@zeroes}{00000}%
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\avr@reg@set{\avr@zeroes}{00001}%
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\avr@reg@set{\avr@zeroes}{00010}%
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\avr@reg@set{\avr@zeroes}{00011}%
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\avr@reg@set{\avr@zeroes}{00100}%
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\avr@reg@set{\avr@zeroes}{00101}%
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\avr@reg@set{\avr@zeroes}{00110}%
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\avr@reg@set{\avr@zeroes}{00111}%
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\avr@reg@set{\avr@zeroes}{01000}%
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\avr@reg@set{\avr@zeroes}{01001}%
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\avr@reg@set{\avr@zeroes}{01010}%
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\avr@reg@set{\avr@zeroes}{01011}%
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\avr@reg@set{\avr@zeroes}{01100}%
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\avr@reg@set{\avr@zeroes}{01101}%
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\avr@reg@set{\avr@zeroes}{01110}%
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\avr@reg@set{\avr@zeroes}{01111}%
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\avr@reg@set{\avr@zeroes}{10000}%
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\avr@reg@set{\avr@zeroes}{10001}%
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\avr@reg@set{\avr@zeroes}{10010}%
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\avr@reg@set{\avr@zeroes}{10011}%
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\avr@reg@set{\avr@zeroes}{10100}%
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\avr@reg@set{\avr@zeroes}{10101}%
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\avr@reg@set{\avr@zeroes}{10110}%
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\avr@reg@set{\avr@zeroes}{10111}%
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\avr@reg@set{\avr@zeroes}{11000}%
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\avr@reg@set{\avr@zeroes}{11001}%
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\avr@reg@set{\avr@zeroes}{11010}%
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\avr@reg@set{\avr@zeroes}{11011}%
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\avr@reg@set{\avr@zeroes}{11100}%
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\avr@reg@set{\avr@zeroes}{11101}%
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\avr@reg@set{\avr@zeroes}{11110}%
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\avr@reg@set{\avr@zeroes}{11111}%
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}
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\csdef{avr@r0}{00000}
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\csdef{avr@r1}{00001}
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\csdef{avr@r2}{00010}
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\csdef{avr@r3}{00011}
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\csdef{avr@r4}{00100}
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\csdef{avr@r5}{00101}
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\csdef{avr@r6}{00110}
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\csdef{avr@r7}{00111}
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\csdef{avr@r8}{01000}
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\csdef{avr@r9}{01001}
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\csdef{avr@r10}{01010}
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\csdef{avr@r11}{01011}
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\csdef{avr@r12}{01100}
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\csdef{avr@r13}{01101}
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\csdef{avr@r14}{01110}
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\csdef{avr@r15}{01111}
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\csdef{avr@r16}{10000}
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\csdef{avr@r17}{10001}
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\csdef{avr@r18}{10010}
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\csdef{avr@r19}{10011}
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\csdef{avr@r20}{10100}
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\csdef{avr@r21}{10101}
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\csdef{avr@r22}{10110}
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\csdef{avr@r23}{10111}
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\csdef{avr@r24}{11000}
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\csdef{avr@r25}{11001}
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\csdef{avr@r26}{11010}
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\csdef{avr@r27}{11011}
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\csdef{avr@r28}{11100}
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\csdef{avr@r29}{11101}
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\csdef{avr@r30}{11110}
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\csdef{avr@r31}{11111}
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%% Code
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\newcount\avr@pc
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\def\avr@pc@init{%
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\avr@pc=0%
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}
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\def\avr@pc@inc{% Increment by one
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\advance \avr@pc by 1\relax%
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\avr@count@overflow{\avr@pc}%
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}
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\def\avr@pc@add#1{% Increment by N
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\advance \avr@pc by #1\relax%
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\avr@count@overflow{\avr@pc}%
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}
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\def\avr@code@get#1{% Result Macro
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\edef#1{\csuse{avr@code@\the\avr@pc}}%
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}
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\def\avr@code@load#1#2{% Result Macro
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\edef#2{\csuse{avr@code@#1}}%
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}
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\def\avr@code@set#1#2{% OpString (16 Bit), Number
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\csxdef{avr@code@#2}{#1}%
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}
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%% RAM
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\newcount\avr@stackptr
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\def\avr@stack@init{%
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\avr@stackptr=0%
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}
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\def\avr@stack@SPL@get#1{%
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\avr@count@tobin@w{\avr@stackptr}{\@@stack}%
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\avr@bin@word@low{\@@stack}{#1}%
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}
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\def\avr@stack@SPH@get#1{%
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\avr@count@tobin@w{\avr@stackptr}{\@@stack}%
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\avr@bin@word@high{\@@stack}{#1}%
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}
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\def\avr@stack@SPL@set#1{%
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\avr@count@tobin@w{\avr@stackptr}{\@@stack}%
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\avr@bin@word@high{\@@stack}{\@@high}%
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\avr@bin@tocount{\@@high #1}{\avr@stackptr}%
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\avr@debug{ SP=\the\avr@stackptr}%
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}
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\def\avr@stack@SPH@set#1{%
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\avr@count@tobin@w{\avr@stackptr}{\@@stack}%
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\avr@bin@word@low{\@@stack}{\@@low}%
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\avr@bin@tocount{#1\@@low}{\avr@stackptr}%
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\avr@debug{ SP=\the\avr@stackptr}%
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}
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\def\avr@mem@init#1{%
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\avr@count@tmpa = #1\relax
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\def\avr@mem@init@helper{%
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\ifnum \avr@count@tmpa > 0%
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\csxdef{avr@mem@\the\avr@count@tmpa}{00000000}%
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\advance \avr@count@tmpa by -1\relax%
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\else%
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\let \avr@mem@init@helper \relax%
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\fi%
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\avr@mem@init@helper%
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}%
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\avr@mem@init@helper%
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}
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\def\avr@mem@set#1#2{% Bitstring, Address (as number)
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\ifnum #2 < 96 % 0x60
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% FIXME
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\avr@error{Not implement access to IO/Regs through memory}%
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\fi%
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\avr@debug{ MEM W *#2=#1}%
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\csxdef{avr@mem@#2}{#1}%
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}
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\def\avr@mem@get#1#2{% Address (as number), Target Macro
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\ifnum #1 < 96 % 0x60
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% FIXME
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\avr@error{Not implement access to IO/Regs through memory}%
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\fi%
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\ifcsdef{avr@mem@#1}{%
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\edef#2{\csuse{avr@mem@#1}}%
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}{%
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\edef#2{00000000}%
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}%
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\avr@debug{ MEM R *#1==#2}%
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}
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