From 2eb4976f3dd6f3c7266bc4c335cab1b9cc301592 Mon Sep 17 00:00:00 2001 From: Mika Tuupola Date: Sun, 20 Nov 2011 18:53:38 +0200 Subject: [PATCH] Code for two daisychained shift registers. --- tpic6b595_shiftout/.dep/main.o.d | 62 ++ tpic6b595_shiftout/.dep/uart_async.o.d | 49 + tpic6b595_shiftout/main.c | 24 +- tpic6b595_shiftout/main.eep | 1 + tpic6b595_shiftout/main.elf | Bin 0 -> 24283 bytes tpic6b595_shiftout/main.h | 2 +- tpic6b595_shiftout/main.hex | 161 +++ tpic6b595_shiftout/main.lss | 1407 ++++++++++++++++++++++++ tpic6b595_shiftout/main.lst | 673 ++++++++++++ tpic6b595_shiftout/main.map | 659 +++++++++++ tpic6b595_shiftout/main.o | Bin 0 -> 6488 bytes tpic6b595_shiftout/main.sym | 112 ++ tpic6b595_shiftout/uart_async.lst | 449 ++++++++ tpic6b595_shiftout/uart_async.o | Bin 0 -> 6136 bytes 14 files changed, 3590 insertions(+), 9 deletions(-) create mode 100644 tpic6b595_shiftout/.dep/main.o.d create mode 100644 tpic6b595_shiftout/.dep/uart_async.o.d create mode 100644 tpic6b595_shiftout/main.eep create mode 100755 tpic6b595_shiftout/main.elf create mode 100644 tpic6b595_shiftout/main.hex create mode 100644 tpic6b595_shiftout/main.lss create mode 100644 tpic6b595_shiftout/main.lst create mode 100644 tpic6b595_shiftout/main.map create mode 100644 tpic6b595_shiftout/main.o create mode 100644 tpic6b595_shiftout/main.sym create mode 100644 tpic6b595_shiftout/uart_async.lst create mode 100644 tpic6b595_shiftout/uart_async.o diff --git a/tpic6b595_shiftout/.dep/main.o.d b/tpic6b595_shiftout/.dep/main.o.d new file mode 100644 index 0000000..115c60d --- /dev/null +++ b/tpic6b595_shiftout/.dep/main.o.d @@ -0,0 +1,62 @@ +main.o: main.c \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/stdlib.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/include/stddef.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/stdio.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/inttypes.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/include/stdint.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/stdint.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/include/stdarg.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h \ + main.h uart.h pins.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/sfr_defs.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/io.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/iom328p.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/portpins.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/common.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/version.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/fuse.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/lock.h \ + digital.h + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/stdlib.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/include/stddef.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/stdio.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/inttypes.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/include/stdint.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/stdint.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/include/stdarg.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h: + +main.h: + +uart.h: + +pins.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/sfr_defs.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/io.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/iom328p.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/portpins.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/common.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/version.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/fuse.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/lock.h: + +digital.h: diff --git a/tpic6b595_shiftout/.dep/uart_async.o.d b/tpic6b595_shiftout/.dep/uart_async.o.d new file mode 100644 index 0000000..80ddbd7 --- /dev/null +++ b/tpic6b595_shiftout/.dep/uart_async.o.d @@ -0,0 +1,49 @@ +uart_async.o: uart_async.c \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/io.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/sfr_defs.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/inttypes.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/include/stdint.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/stdint.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/iom328p.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/portpins.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/common.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/version.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/fuse.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/lock.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/interrupt.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/stdio.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/include/stdarg.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/include/stddef.h \ + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/setbaud.h + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/io.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/sfr_defs.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/inttypes.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/include/stdint.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/stdint.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/iom328p.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/portpins.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/common.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/version.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/fuse.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/lock.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/avr/interrupt.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/stdio.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/include/stdarg.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/include/stddef.h: + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/setbaud.h: diff --git a/tpic6b595_shiftout/main.c b/tpic6b595_shiftout/main.c index bf094f8..9b41b8d 100644 --- a/tpic6b595_shiftout/main.c +++ b/tpic6b595_shiftout/main.c @@ -1,5 +1,5 @@ /* - * Code to write data to TPIC6B595 SIPO shift register. + * Code to write data to two daisychained TPIC6B595 SIPO shift registers. * * The TPIC6B595 is a monolithic, high-voltage, medium-current power 8-bit * shift register designed for use in systems that require relatively high @@ -39,9 +39,9 @@ #include "pins.h" #include "digital.h" -#define LATCH 8 /* RCK */ -#define CLOCK 12 /* SRCK */ +#define LATCH 10 /* RCK */ #define DATA 11 /* SER IN */ +#define CLOCK 13 /* SRCK */ static void init(void) { pin_mode(LATCH, OUTPUT); @@ -72,24 +72,32 @@ int main(void) { stdout = &uart_output; stdin = &uart_input; - uint8_t binary[9]; + char binary[17]; + + /* Show pattern for 5 seconds. */ + shift_out(0b10101010); + shift_out(0b11110000); + digital_write(LATCH, LOW); + digital_write(LATCH, HIGH); + _delay_ms(5000); while (1) { - for(uint8_t i = 0; i < 256; i++) { + for(uint16_t i = 0; i < 0xffff; i++) { /* Print the number to serial for debugging. */ itoa(i, binary, 2); printf("%s %d \n", binary, i); - /* Shift current number to shift register. */ - shift_out(i); + /* Shift high byte first to shift register. */ + shift_out(i >> 8); + shift_out(i & 0xff); /* Pulse latch to transfer data from shift registers */ /* to storage registers (should this be inside shift_out()?). */ digital_write(LATCH, LOW); digital_write(LATCH, HIGH); - _delay_ms(250); + _delay_ms(50); } } return 0; diff --git a/tpic6b595_shiftout/main.eep b/tpic6b595_shiftout/main.eep new file mode 100644 index 0000000..1996e8f --- /dev/null +++ b/tpic6b595_shiftout/main.eep @@ -0,0 +1 @@ +:00000001FF diff --git a/tpic6b595_shiftout/main.elf b/tpic6b595_shiftout/main.elf new file mode 100755 index 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z_x-O~KmBQrb$uQ7P4`d@8T54}BA8TC1Oh43)Q2;ZuJ4jGF#(%ng15dho-b z-;?&7?)ix#Px_w+od$g=roLZ;roVuoi}W1>t=fA6v})f!K-0d1=5w;=Tpzx!sr5VE zGZ3_@FBNp1J%HR)p3c4ndcUB^CXG!7?Sg$tNF)8ZefaZ1Tlz?TG10KWY7bu@`PF^s zb)c>H%%s1$5C0C(G$yB-<yUdnwDlCqXmTBqZW7V(HsZ>mvChpso2G zC(i753ZLw!S60^EjpVyP?>7|?{}a$weTh$B1UHy`q6dSH=+{{WXxb0H0~xB{MW9uE z6G2;73g(yGKKyxo=&SnB^mkjTzBQnoO8=uz!fAg=Pi|B`{SlCA|BgO1&9!0?fjrr> z4|JqHoP8g3q`%nMBcRpt4}zvcaJtA}&w^I{d063-zkbyx|L^+HZ-cI~2gJ&nfd2Wn zKK#?5X{MI{jpKr6`;^J#{vrkz}tLZU1_<%8%yhIOrqDf5|MZ2kr(7XUrFWKH8mv_l@oo{rRDUi z3B3|l<*uP+M11j_o@3_C2$v7dj-Wbbw_}OHZ^*-M`$VN(OZDmzWd1EOm4-;_{?ue8Nkp`HI6AV0a zSho5~#iNYWmpxI@P35S+BLK43&qWxA1Lh$OJcUylUsVl`BIplErOF(7Yfg_m^a~J3 zR*mQ-cyX^25wn8X7b8nVv*BT+&`(>K<&fulDaxKiMbb|~M6Af7#uaBFqE}ca8q&%v zD#vo_WCc%&;K|nEljsL(%Uk973L#xuir%rNmr3: + 0: 0c 94 34 00 jmp 0x68 ; 0x68 <__ctors_end> + 4: 0c 94 51 00 jmp 0xa2 ; 0xa2 <__bad_interrupt> + 8: 0c 94 51 00 jmp 0xa2 ; 0xa2 <__bad_interrupt> + c: 0c 94 51 00 jmp 0xa2 ; 0xa2 <__bad_interrupt> + 10: 0c 94 51 00 jmp 0xa2 ; 0xa2 <__bad_interrupt> + 14: 0c 94 51 00 jmp 0xa2 ; 0xa2 <__bad_interrupt> + 18: 0c 94 51 00 jmp 0xa2 ; 0xa2 <__bad_interrupt> + 1c: 0c 94 51 00 jmp 0xa2 ; 0xa2 <__bad_interrupt> + 20: 0c 94 51 00 jmp 0xa2 ; 0xa2 <__bad_interrupt> + 24: 0c 94 51 00 jmp 0xa2 ; 0xa2 <__bad_interrupt> + 28: 0c 94 51 00 jmp 0xa2 ; 0xa2 <__bad_interrupt> + 2c: 0c 94 51 00 jmp 0xa2 ; 0xa2 <__bad_interrupt> + 30: 0c 94 51 00 jmp 0xa2 ; 0xa2 <__bad_interrupt> + 34: 0c 94 51 00 jmp 0xa2 ; 0xa2 <__bad_interrupt> + 38: 0c 94 51 00 jmp 0xa2 ; 0xa2 <__bad_interrupt> + 3c: 0c 94 51 00 jmp 0xa2 ; 0xa2 <__bad_interrupt> + 40: 0c 94 51 00 jmp 0xa2 ; 0xa2 <__bad_interrupt> + 44: 0c 94 51 00 jmp 0xa2 ; 0xa2 <__bad_interrupt> + 48: 0c 94 c9 00 jmp 0x192 ; 0x192 <__vector_18> + 4c: 0c 94 09 01 jmp 0x212 ; 0x212 <__vector_19> + 50: 0c 94 51 00 jmp 0xa2 ; 0xa2 <__bad_interrupt> + 54: 0c 94 51 00 jmp 0xa2 ; 0xa2 <__bad_interrupt> + 58: 0c 94 51 00 jmp 0xa2 ; 0xa2 <__bad_interrupt> + 5c: 0c 94 51 00 jmp 0xa2 ; 0xa2 <__bad_interrupt> + 60: 0c 94 51 00 jmp 0xa2 ; 0xa2 <__bad_interrupt> + 64: 0c 94 51 00 jmp 0xa2 ; 0xa2 <__bad_interrupt> + +00000068 <__ctors_end>: + 68: 11 24 eor r1, r1 + 6a: 1f be out 0x3f, r1 ; 63 + 6c: cf ef ldi r28, 0xFF ; 255 + 6e: d8 e0 ldi r29, 0x08 ; 8 + 70: de bf out 0x3e, r29 ; 62 + 72: cd bf out 0x3d, r28 ; 61 + +00000074 <__do_copy_data>: + 74: 11 e0 ldi r17, 0x01 ; 1 + 76: a0 e0 ldi r26, 0x00 ; 0 + 78: b1 e0 ldi r27, 0x01 ; 1 + 7a: e8 ec ldi r30, 0xC8 ; 200 + 7c: f9 e0 ldi r31, 0x09 ; 9 + 7e: 02 c0 rjmp .+4 ; 0x84 <__do_copy_data+0x10> + 80: 05 90 lpm r0, Z+ + 82: 0d 92 st X+, r0 + 84: a4 32 cpi r26, 0x24 ; 36 + 86: b1 07 cpc r27, r17 + 88: d9 f7 brne .-10 ; 0x80 <__do_copy_data+0xc> + +0000008a <__do_clear_bss>: + 8a: 15 e0 ldi r17, 0x05 ; 5 + 8c: a4 e2 ldi r26, 0x24 ; 36 + 8e: b1 e0 ldi r27, 0x01 ; 1 + 90: 01 c0 rjmp .+2 ; 0x94 <.do_clear_bss_start> + +00000092 <.do_clear_bss_loop>: + 92: 1d 92 st X+, r1 + +00000094 <.do_clear_bss_start>: + 94: a2 37 cpi r26, 0x72 ; 114 + 96: b1 07 cpc r27, r17 + 98: e1 f7 brne .-8 ; 0x92 <.do_clear_bss_loop> + 9a: 0e 94 4b 01 call 0x296 ; 0x296
+ 9e: 0c 94 e2 04 jmp 0x9c4 ; 0x9c4 <_exit> + +000000a2 <__bad_interrupt>: + a2: 0c 94 00 00 jmp 0 ; 0x0 <__vectors> + +000000a6 : + pin_mode(CLOCK, OUTPUT); + pin_mode(DATA, OUTPUT); +} + +/* Assumes MSB first. */ +void shift_out(uint8_t data) { + a6: 27 e0 ldi r18, 0x07 ; 7 + a8: 30 e0 ldi r19, 0x00 ; 0 + for(uint8_t i = 0; i < 8; i++) { + /* Write bit to data port. */ + if (0 == (data & _BV(7 - i))) { + aa: 90 e0 ldi r25, 0x00 ; 0 + ac: ac 01 movw r20, r24 + ae: 02 2e mov r0, r18 + b0: 02 c0 rjmp .+4 ; 0xb6 + b2: 55 95 asr r21 + b4: 47 95 ror r20 + b6: 0a 94 dec r0 + b8: e2 f7 brpl .-8 ; 0xb2 + ba: 40 fd sbrc r20, 0 + bc: 02 c0 rjmp .+4 ; 0xc2 + digital_write(DATA, LOW); + be: 2b 98 cbi 0x05, 3 ; 5 + c0: 01 c0 rjmp .+2 ; 0xc4 + } else { + digital_write(DATA, HIGH); + c2: 2b 9a sbi 0x05, 3 ; 5 + } + + /* Pulse clock input to write next bit. */ + digital_write(CLOCK, LOW); + c4: 2d 98 cbi 0x05, 5 ; 5 + digital_write(CLOCK, HIGH); + c6: 2d 9a sbi 0x05, 5 ; 5 + c8: 21 50 subi r18, 0x01 ; 1 + ca: 30 40 sbci r19, 0x00 ; 0 + pin_mode(DATA, OUTPUT); +} + +/* Assumes MSB first. */ +void shift_out(uint8_t data) { + for(uint8_t i = 0; i < 8; i++) { + cc: 4f ef ldi r20, 0xFF ; 255 + ce: 2f 3f cpi r18, 0xFF ; 255 + d0: 34 07 cpc r19, r20 + d2: 61 f7 brne .-40 ; 0xac + + /* Pulse clock input to write next bit. */ + digital_write(CLOCK, LOW); + digital_write(CLOCK, HIGH); + } +} + d4: 08 95 ret + +000000d6 : + +/* http://www.cs.mun.ca/~rod/Winter2007/4723/notes/serial/serial.html */ + +void uart_init(void) { + + tx_buffer.start = 0; + d6: 10 92 25 05 sts 0x0525, r1 + da: 10 92 24 05 sts 0x0524, r1 + tx_buffer.end = 0; + de: 10 92 27 05 sts 0x0527, r1 + e2: 10 92 26 05 sts 0x0526, r1 + + rx_buffer.start = 0; + e6: 10 92 69 05 sts 0x0569, r1 + ea: 10 92 68 05 sts 0x0568, r1 + rx_buffer.end = 0; + ee: 10 92 6b 05 sts 0x056B, r1 + f2: 10 92 6a 05 sts 0x056A, r1 + + UBRR0H = UBRRH_VALUE; + f6: 10 92 c5 00 sts 0x00C5, r1 + UBRR0L = UBRRL_VALUE; + fa: 87 e6 ldi r24, 0x67 ; 103 + fc: 80 93 c4 00 sts 0x00C4, r24 + + UCSR0C = _BV(UCSZ01) | _BV(UCSZ00); /* 8-bit data */ + 100: 86 e0 ldi r24, 0x06 ; 6 + 102: 80 93 c2 00 sts 0x00C2, r24 + UCSR0B = _BV(RXEN0) | _BV(TXEN0); /* Enable RX and TX */ + 106: 88 e1 ldi r24, 0x18 ; 24 + 108: 80 93 c1 00 sts 0x00C1, r24 + + sei(); + 10c: 78 94 sei +} + 10e: 08 95 ret + +00000110 : + +int uart_putchar(char c, FILE *stream) { + 110: 1f 93 push r17 + 112: 18 2f mov r17, r24 + if (c == '\n') { + 114: 8a 30 cpi r24, 0x0A ; 10 + 116: 19 f4 brne .+6 ; 0x11e + uart_putchar('\r', stream); + 118: 8d e0 ldi r24, 0x0D ; 13 + 11a: 0e 94 88 00 call 0x110 ; 0x110 + } + + int write_pointer = (tx_buffer.end + 1) % UART_TX_BUFFER_SIZE; + 11e: 20 91 26 05 lds r18, 0x0526 + 122: 30 91 27 05 lds r19, 0x0527 + 126: c9 01 movw r24, r18 + 128: 01 96 adiw r24, 0x01 ; 1 + 12a: 60 e0 ldi r22, 0x00 ; 0 + 12c: 72 e0 ldi r23, 0x02 ; 2 + 12e: 0e 94 be 01 call 0x37c ; 0x37c <__divmodhi4> + + if (write_pointer != tx_buffer.start){ + 132: 40 91 24 05 lds r20, 0x0524 + 136: 50 91 25 05 lds r21, 0x0525 + 13a: 84 17 cp r24, r20 + 13c: 95 07 cpc r25, r21 + 13e: 81 f0 breq .+32 ; 0x160 + tx_buffer.buffer[tx_buffer.end] = c; + 140: f9 01 movw r30, r18 + 142: ee 0f add r30, r30 + 144: ff 1f adc r31, r31 + 146: ec 5d subi r30, 0xDC ; 220 + 148: fe 4f sbci r31, 0xFE ; 254 + 14a: 10 83 st Z, r17 + 14c: 11 82 std Z+1, r1 ; 0x01 + tx_buffer.end = write_pointer; + 14e: 90 93 27 05 sts 0x0527, r25 + 152: 80 93 26 05 sts 0x0526, r24 + + /* Data available. Enable the transmit interrupt for serial port 0. */ + UCSR0B |= _BV(UDRIE0); + 156: 80 91 c1 00 lds r24, 0x00C1 + 15a: 80 62 ori r24, 0x20 ; 32 + 15c: 80 93 c1 00 sts 0x00C1, r24 + } + + return 0; +} + 160: 80 e0 ldi r24, 0x00 ; 0 + 162: 90 e0 ldi r25, 0x00 ; 0 + 164: 1f 91 pop r17 + 166: 08 95 ret + +00000168 : + +int uart_getchar(FILE *stream) { + int read_pointer = (rx_buffer.start + 1) % UART_RX_BUFFER_SIZE; + 168: 80 91 68 05 lds r24, 0x0568 + 16c: 90 91 69 05 lds r25, 0x0569 + 170: 01 96 adiw r24, 0x01 ; 1 + 172: 60 e2 ldi r22, 0x20 ; 32 + 174: 70 e0 ldi r23, 0x00 ; 0 + 176: 0e 94 be 01 call 0x37c ; 0x37c <__divmodhi4> + + rx_buffer.start = read_pointer; + 17a: 90 93 69 05 sts 0x0569, r25 + 17e: 80 93 68 05 sts 0x0568, r24 + return rx_buffer.buffer[read_pointer]; + 182: fc 01 movw r30, r24 + 184: ee 0f add r30, r30 + 186: ff 1f adc r31, r31 + 188: e8 5d subi r30, 0xD8 ; 216 + 18a: fa 4f sbci r31, 0xFA ; 250 +} + 18c: 80 81 ld r24, Z + 18e: 91 81 ldd r25, Z+1 ; 0x01 + 190: 08 95 ret + +00000192 <__vector_18>: + +ISR(USART_RX_vect) { + 192: 1f 92 push r1 + 194: 0f 92 push r0 + 196: 0f b6 in r0, 0x3f ; 63 + 198: 0f 92 push r0 + 19a: 11 24 eor r1, r1 + 19c: 2f 93 push r18 + 19e: 3f 93 push r19 + 1a0: 4f 93 push r20 + 1a2: 5f 93 push r21 + 1a4: 6f 93 push r22 + 1a6: 7f 93 push r23 + 1a8: 8f 93 push r24 + 1aa: 9f 93 push r25 + 1ac: af 93 push r26 + 1ae: bf 93 push r27 + 1b0: ef 93 push r30 + 1b2: ff 93 push r31 + int write_pointer = (rx_buffer.end + 1) % UART_RX_BUFFER_SIZE; + 1b4: 20 91 6a 05 lds r18, 0x056A + 1b8: 30 91 6b 05 lds r19, 0x056B + 1bc: c9 01 movw r24, r18 + 1be: 01 96 adiw r24, 0x01 ; 1 + 1c0: 60 e2 ldi r22, 0x20 ; 32 + 1c2: 70 e0 ldi r23, 0x00 ; 0 + 1c4: 0e 94 be 01 call 0x37c ; 0x37c <__divmodhi4> + + /* Add next byte to ringbuffer if it has space available. */ + if (write_pointer != rx_buffer.start){ + 1c8: 40 91 68 05 lds r20, 0x0568 + 1cc: 50 91 69 05 lds r21, 0x0569 + 1d0: 84 17 cp r24, r20 + 1d2: 95 07 cpc r25, r21 + 1d4: 69 f0 breq .+26 ; 0x1f0 <__vector_18+0x5e> + rx_buffer.buffer[rx_buffer.end] = UDR0; + 1d6: 40 91 c6 00 lds r20, 0x00C6 + 1da: f9 01 movw r30, r18 + 1dc: ee 0f add r30, r30 + 1de: ff 1f adc r31, r31 + 1e0: e8 5d subi r30, 0xD8 ; 216 + 1e2: fa 4f sbci r31, 0xFA ; 250 + 1e4: 40 83 st Z, r20 + 1e6: 11 82 std Z+1, r1 ; 0x01 + rx_buffer.end = write_pointer; + 1e8: 90 93 6b 05 sts 0x056B, r25 + 1ec: 80 93 6a 05 sts 0x056A, r24 + } +} + 1f0: ff 91 pop r31 + 1f2: ef 91 pop r30 + 1f4: bf 91 pop r27 + 1f6: af 91 pop r26 + 1f8: 9f 91 pop r25 + 1fa: 8f 91 pop r24 + 1fc: 7f 91 pop r23 + 1fe: 6f 91 pop r22 + 200: 5f 91 pop r21 + 202: 4f 91 pop r20 + 204: 3f 91 pop r19 + 206: 2f 91 pop r18 + 208: 0f 90 pop r0 + 20a: 0f be out 0x3f, r0 ; 63 + 20c: 0f 90 pop r0 + 20e: 1f 90 pop r1 + 210: 18 95 reti + +00000212 <__vector_19>: + +ISR(USART_UDRE_vect){ + 212: 1f 92 push r1 + 214: 0f 92 push r0 + 216: 0f b6 in r0, 0x3f ; 63 + 218: 0f 92 push r0 + 21a: 11 24 eor r1, r1 + 21c: 2f 93 push r18 + 21e: 3f 93 push r19 + 220: 5f 93 push r21 + 222: 6f 93 push r22 + 224: 7f 93 push r23 + 226: 8f 93 push r24 + 228: 9f 93 push r25 + 22a: af 93 push r26 + 22c: bf 93 push r27 + 22e: ef 93 push r30 + 230: ff 93 push r31 + int read_pointer = (tx_buffer.start + 1) % UART_TX_BUFFER_SIZE; + 232: 80 91 24 05 lds r24, 0x0524 + 236: 90 91 25 05 lds r25, 0x0525 + 23a: 01 96 adiw r24, 0x01 ; 1 + 23c: 60 e0 ldi r22, 0x00 ; 0 + 23e: 72 e0 ldi r23, 0x02 ; 2 + 240: 0e 94 be 01 call 0x37c ; 0x37c <__divmodhi4> + + /* Transmit next byte if data available in ringbuffer. */ + if (read_pointer != tx_buffer.end) { + 244: 20 91 26 05 lds r18, 0x0526 + 248: 30 91 27 05 lds r19, 0x0527 + 24c: 82 17 cp r24, r18 + 24e: 93 07 cpc r25, r19 + 250: 69 f0 breq .+26 ; 0x26c <__vector_19+0x5a> + UDR0 = tx_buffer.buffer[read_pointer]; + 252: fc 01 movw r30, r24 + 254: ee 0f add r30, r30 + 256: ff 1f adc r31, r31 + 258: ec 5d subi r30, 0xDC ; 220 + 25a: fe 4f sbci r31, 0xFE ; 254 + 25c: 20 81 ld r18, Z + 25e: 20 93 c6 00 sts 0x00C6, r18 + tx_buffer.start = read_pointer; + 262: 90 93 25 05 sts 0x0525, r25 + 266: 80 93 24 05 sts 0x0524, r24 + 26a: 05 c0 rjmp .+10 ; 0x276 <__vector_19+0x64> + } else { + /* Nothing to send. Disable the transmit interrupt for serial port 0. */ + UCSR0B &= ~_BV(UDRIE0); + 26c: 80 91 c1 00 lds r24, 0x00C1 + 270: 8f 7d andi r24, 0xDF ; 223 + 272: 80 93 c1 00 sts 0x00C1, r24 + } +} + 276: ff 91 pop r31 + 278: ef 91 pop r30 + 27a: bf 91 pop r27 + 27c: af 91 pop r26 + 27e: 9f 91 pop r25 + 280: 8f 91 pop r24 + 282: 7f 91 pop r23 + 284: 6f 91 pop r22 + 286: 5f 91 pop r21 + 288: 3f 91 pop r19 + 28a: 2f 91 pop r18 + 28c: 0f 90 pop r0 + 28e: 0f be out 0x3f, r0 ; 63 + 290: 0f 90 pop r0 + 292: 1f 90 pop r1 + 294: 18 95 reti + +00000296
: + +int main(void) { + 296: cf 93 push r28 + 298: df 93 push r29 + 29a: cd b7 in r28, 0x3d ; 61 + 29c: de b7 in r29, 0x3e ; 62 + 29e: 61 97 sbiw r28, 0x11 ; 17 + 2a0: 0f b6 in r0, 0x3f ; 63 + 2a2: f8 94 cli + 2a4: de bf out 0x3e, r29 ; 62 + 2a6: 0f be out 0x3f, r0 ; 63 + 2a8: cd bf out 0x3d, r28 ; 61 +#define LATCH 10 /* RCK */ +#define DATA 11 /* SER IN */ +#define CLOCK 13 /* SRCK */ + +static void init(void) { + pin_mode(LATCH, OUTPUT); + 2aa: 22 9a sbi 0x04, 2 ; 4 + pin_mode(CLOCK, OUTPUT); + 2ac: 25 9a sbi 0x04, 5 ; 4 + pin_mode(DATA, OUTPUT); + 2ae: 23 9a sbi 0x04, 3 ; 4 +} + +int main(void) { + + init(); + uart_init(); + 2b0: 0e 94 6b 00 call 0xd6 ; 0xd6 + stdout = &uart_output; + 2b4: 86 e1 ldi r24, 0x16 ; 22 + 2b6: 91 e0 ldi r25, 0x01 ; 1 + 2b8: 90 93 6f 05 sts 0x056F, r25 + 2bc: 80 93 6e 05 sts 0x056E, r24 + stdin = &uart_input; + 2c0: 88 e0 ldi r24, 0x08 ; 8 + 2c2: 91 e0 ldi r25, 0x01 ; 1 + 2c4: 90 93 6d 05 sts 0x056D, r25 + 2c8: 80 93 6c 05 sts 0x056C, r24 + + char binary[17]; + + /* Show pattern for 5 seconds. */ + shift_out(0b10101010); + 2cc: 8a ea ldi r24, 0xAA ; 170 + 2ce: 0e 94 53 00 call 0xa6 ; 0xa6 + shift_out(0b11110000); + 2d2: 80 ef ldi r24, 0xF0 ; 240 + 2d4: 0e 94 53 00 call 0xa6 ; 0xa6 + digital_write(LATCH, LOW); + 2d8: 2a 98 cbi 0x05, 2 ; 5 + digital_write(LATCH, HIGH); + 2da: 2a 9a sbi 0x05, 2 ; 5 + 2dc: 80 e5 ldi r24, 0x50 ; 80 + 2de: 93 ec ldi r25, 0xC3 ; 195 + milliseconds can be achieved. + */ +void +_delay_loop_2(uint16_t __count) +{ + __asm__ volatile ( + 2e0: 20 e9 ldi r18, 0x90 ; 144 + 2e2: 31 e0 ldi r19, 0x01 ; 1 + 2e4: f9 01 movw r30, r18 + 2e6: 31 97 sbiw r30, 0x01 ; 1 + 2e8: f1 f7 brne .-4 ; 0x2e6 + 2ea: 01 97 sbiw r24, 0x01 ; 1 + __ticks = 1; + else if (__tmp > 65535) + { + // __ticks = requested delay in 1/10 ms + __ticks = (uint16_t) (__ms * 10.0); + while(__ticks) + 2ec: d9 f7 brne .-10 ; 0x2e4 + 2ee: 00 e0 ldi r16, 0x00 ; 0 + 2f0: 10 e0 ldi r17, 0x00 ; 0 + + while (1) { + for(uint16_t i = 0; i < 0xffff; i++) { + + /* Print the number to serial for debugging. */ + itoa(i, binary, 2); + 2f2: 7e 01 movw r14, r28 + 2f4: 08 94 sec + 2f6: e1 1c adc r14, r1 + 2f8: f1 1c adc r15, r1 + printf("%s %d \n", binary, i); + 2fa: 80 e0 ldi r24, 0x00 ; 0 + 2fc: c8 2e mov r12, r24 + 2fe: 81 e0 ldi r24, 0x01 ; 1 + 300: d8 2e mov r13, r24 + 302: 90 e9 ldi r25, 0x90 ; 144 + 304: a9 2e mov r10, r25 + 306: 91 e0 ldi r25, 0x01 ; 1 + 308: b9 2e mov r11, r25 + + while (1) { + for(uint16_t i = 0; i < 0xffff; i++) { + + /* Print the number to serial for debugging. */ + itoa(i, binary, 2); + 30a: c8 01 movw r24, r16 + 30c: b7 01 movw r22, r14 + 30e: 42 e0 ldi r20, 0x02 ; 2 + 310: 50 e0 ldi r21, 0x00 ; 0 + 312: 0e 94 e5 01 call 0x3ca ; 0x3ca + printf("%s %d \n", binary, i); + 316: 00 d0 rcall .+0 ; 0x318 + 318: 00 d0 rcall .+0 ; 0x31a + 31a: 00 d0 rcall .+0 ; 0x31c + 31c: ed b7 in r30, 0x3d ; 61 + 31e: fe b7 in r31, 0x3e ; 62 + 320: 31 96 adiw r30, 0x01 ; 1 + 322: ad b7 in r26, 0x3d ; 61 + 324: be b7 in r27, 0x3e ; 62 + 326: 12 96 adiw r26, 0x02 ; 2 + 328: dc 92 st X, r13 + 32a: ce 92 st -X, r12 + 32c: 11 97 sbiw r26, 0x01 ; 1 + 32e: f3 82 std Z+3, r15 ; 0x03 + 330: e2 82 std Z+2, r14 ; 0x02 + 332: 15 83 std Z+5, r17 ; 0x05 + 334: 04 83 std Z+4, r16 ; 0x04 + 336: 0e 94 06 02 call 0x40c ; 0x40c + + /* Shift high byte first to shift register. */ + shift_out(i >> 8); + 33a: 8d b7 in r24, 0x3d ; 61 + 33c: 9e b7 in r25, 0x3e ; 62 + 33e: 06 96 adiw r24, 0x06 ; 6 + 340: 0f b6 in r0, 0x3f ; 63 + 342: f8 94 cli + 344: 9e bf out 0x3e, r25 ; 62 + 346: 0f be out 0x3f, r0 ; 63 + 348: 8d bf out 0x3d, r24 ; 61 + 34a: 81 2f mov r24, r17 + 34c: 0e 94 53 00 call 0xa6 ; 0xa6 + shift_out(i & 0xff); + 350: 80 2f mov r24, r16 + 352: 0e 94 53 00 call 0xa6 ; 0xa6 + + /* Pulse latch to transfer data from shift registers */ + /* to storage registers (should this be inside shift_out()?). */ + digital_write(LATCH, LOW); + 356: 2a 98 cbi 0x05, 2 ; 5 + digital_write(LATCH, HIGH); + 358: 2a 9a sbi 0x05, 2 ; 5 + 35a: 24 ef ldi r18, 0xF4 ; 244 + 35c: 31 e0 ldi r19, 0x01 ; 1 + 35e: c5 01 movw r24, r10 + 360: 01 97 sbiw r24, 0x01 ; 1 + 362: f1 f7 brne .-4 ; 0x360 + 364: 21 50 subi r18, 0x01 ; 1 + 366: 30 40 sbci r19, 0x00 ; 0 + 368: d1 f7 brne .-12 ; 0x35e + digital_write(LATCH, LOW); + digital_write(LATCH, HIGH); + _delay_ms(5000); + + while (1) { + for(uint16_t i = 0; i < 0xffff; i++) { + 36a: 0f 5f subi r16, 0xFF ; 255 + 36c: 1f 4f sbci r17, 0xFF ; 255 + 36e: 9f ef ldi r25, 0xFF ; 255 + 370: 0f 3f cpi r16, 0xFF ; 255 + 372: 19 07 cpc r17, r25 + 374: 51 f6 brne .-108 ; 0x30a + 376: 00 e0 ldi r16, 0x00 ; 0 + 378: 10 e0 ldi r17, 0x00 ; 0 + 37a: c7 cf rjmp .-114 ; 0x30a + +0000037c <__divmodhi4>: + 37c: 97 fb bst r25, 7 + 37e: 09 2e mov r0, r25 + 380: 07 26 eor r0, r23 + 382: 0a d0 rcall .+20 ; 0x398 <__divmodhi4_neg1> + 384: 77 fd sbrc r23, 7 + 386: 04 d0 rcall .+8 ; 0x390 <__divmodhi4_neg2> + 388: 0c d0 rcall .+24 ; 0x3a2 <__udivmodhi4> + 38a: 06 d0 rcall .+12 ; 0x398 <__divmodhi4_neg1> + 38c: 00 20 and r0, r0 + 38e: 1a f4 brpl .+6 ; 0x396 <__divmodhi4_exit> + +00000390 <__divmodhi4_neg2>: + 390: 70 95 com r23 + 392: 61 95 neg r22 + 394: 7f 4f sbci r23, 0xFF ; 255 + +00000396 <__divmodhi4_exit>: + 396: 08 95 ret + +00000398 <__divmodhi4_neg1>: + 398: f6 f7 brtc .-4 ; 0x396 <__divmodhi4_exit> + 39a: 90 95 com r25 + 39c: 81 95 neg r24 + 39e: 9f 4f sbci r25, 0xFF ; 255 + 3a0: 08 95 ret + +000003a2 <__udivmodhi4>: + 3a2: aa 1b sub r26, r26 + 3a4: bb 1b sub r27, r27 + 3a6: 51 e1 ldi r21, 0x11 ; 17 + 3a8: 07 c0 rjmp .+14 ; 0x3b8 <__udivmodhi4_ep> + +000003aa <__udivmodhi4_loop>: + 3aa: aa 1f adc r26, r26 + 3ac: bb 1f adc r27, r27 + 3ae: a6 17 cp r26, r22 + 3b0: b7 07 cpc r27, r23 + 3b2: 10 f0 brcs .+4 ; 0x3b8 <__udivmodhi4_ep> + 3b4: a6 1b sub r26, r22 + 3b6: b7 0b sbc r27, r23 + +000003b8 <__udivmodhi4_ep>: + 3b8: 88 1f adc r24, r24 + 3ba: 99 1f adc r25, r25 + 3bc: 5a 95 dec r21 + 3be: a9 f7 brne .-22 ; 0x3aa <__udivmodhi4_loop> + 3c0: 80 95 com r24 + 3c2: 90 95 com r25 + 3c4: bc 01 movw r22, r24 + 3c6: cd 01 movw r24, r26 + 3c8: 08 95 ret + +000003ca : + 3ca: fb 01 movw r30, r22 + 3cc: 9f 01 movw r18, r30 + 3ce: e8 94 clt + 3d0: 42 30 cpi r20, 0x02 ; 2 + 3d2: c4 f0 brlt .+48 ; 0x404 + 3d4: 45 32 cpi r20, 0x25 ; 37 + 3d6: b4 f4 brge .+44 ; 0x404 + 3d8: 4a 30 cpi r20, 0x0A ; 10 + 3da: 29 f4 brne .+10 ; 0x3e6 + 3dc: 97 fb bst r25, 7 + 3de: 1e f4 brtc .+6 ; 0x3e6 + 3e0: 90 95 com r25 + 3e2: 81 95 neg r24 + 3e4: 9f 4f sbci r25, 0xFF ; 255 + 3e6: 64 2f mov r22, r20 + 3e8: 77 27 eor r23, r23 + 3ea: 0e 94 d1 01 call 0x3a2 ; 0x3a2 <__udivmodhi4> + 3ee: 80 5d subi r24, 0xD0 ; 208 + 3f0: 8a 33 cpi r24, 0x3A ; 58 + 3f2: 0c f0 brlt .+2 ; 0x3f6 + 3f4: 89 5d subi r24, 0xD9 ; 217 + 3f6: 81 93 st Z+, r24 + 3f8: cb 01 movw r24, r22 + 3fa: 00 97 sbiw r24, 0x00 ; 0 + 3fc: a1 f7 brne .-24 ; 0x3e6 + 3fe: 16 f4 brtc .+4 ; 0x404 + 400: 5d e2 ldi r21, 0x2D ; 45 + 402: 51 93 st Z+, r21 + 404: 10 82 st Z, r1 + 406: c9 01 movw r24, r18 + 408: 0c 94 11 04 jmp 0x822 ; 0x822 + +0000040c : + 40c: a0 e0 ldi r26, 0x00 ; 0 + 40e: b0 e0 ldi r27, 0x00 ; 0 + 410: ec e0 ldi r30, 0x0C ; 12 + 412: f2 e0 ldi r31, 0x02 ; 2 + 414: 0c 94 bb 04 jmp 0x976 ; 0x976 <__prologue_saves__+0x20> + 418: fe 01 movw r30, r28 + 41a: 35 96 adiw r30, 0x05 ; 5 + 41c: 61 91 ld r22, Z+ + 41e: 71 91 ld r23, Z+ + 420: 80 91 6e 05 lds r24, 0x056E + 424: 90 91 6f 05 lds r25, 0x056F + 428: af 01 movw r20, r30 + 42a: 0e 94 1b 02 call 0x436 ; 0x436 + 42e: 20 96 adiw r28, 0x00 ; 0 + 430: e2 e0 ldi r30, 0x02 ; 2 + 432: 0c 94 d7 04 jmp 0x9ae ; 0x9ae <__epilogue_restores__+0x20> + +00000436 : + 436: ad e0 ldi r26, 0x0D ; 13 + 438: b0 e0 ldi r27, 0x00 ; 0 + 43a: e1 e2 ldi r30, 0x21 ; 33 + 43c: f2 e0 ldi r31, 0x02 ; 2 + 43e: 0c 94 ab 04 jmp 0x956 ; 0x956 <__prologue_saves__> + 442: 3c 01 movw r6, r24 + 444: 7d 87 std Y+13, r23 ; 0x0d + 446: 6c 87 std Y+12, r22 ; 0x0c + 448: 5a 01 movw r10, r20 + 44a: fc 01 movw r30, r24 + 44c: 17 82 std Z+7, r1 ; 0x07 + 44e: 16 82 std Z+6, r1 ; 0x06 + 450: 83 81 ldd r24, Z+3 ; 0x03 + 452: 81 ff sbrs r24, 1 + 454: ca c1 rjmp .+916 ; 0x7ea + 456: 3f e3 ldi r19, 0x3F ; 63 + 458: c3 2e mov r12, r19 + 45a: 2e 01 movw r4, r28 + 45c: 08 94 sec + 45e: 41 1c adc r4, r1 + 460: 51 1c adc r5, r1 + 462: f3 01 movw r30, r6 + 464: 93 81 ldd r25, Z+3 ; 0x03 + 466: ec 85 ldd r30, Y+12 ; 0x0c + 468: fd 85 ldd r31, Y+13 ; 0x0d + 46a: 93 fd sbrc r25, 3 + 46c: 85 91 lpm r24, Z+ + 46e: 93 ff sbrs r25, 3 + 470: 81 91 ld r24, Z+ + 472: fd 87 std Y+13, r31 ; 0x0d + 474: ec 87 std Y+12, r30 ; 0x0c + 476: 88 23 and r24, r24 + 478: 09 f4 brne .+2 ; 0x47c + 47a: b3 c1 rjmp .+870 ; 0x7e2 + 47c: 85 32 cpi r24, 0x25 ; 37 + 47e: 41 f4 brne .+16 ; 0x490 + 480: 93 fd sbrc r25, 3 + 482: 85 91 lpm r24, Z+ + 484: 93 ff sbrs r25, 3 + 486: 81 91 ld r24, Z+ + 488: fd 87 std Y+13, r31 ; 0x0d + 48a: ec 87 std Y+12, r30 ; 0x0c + 48c: 85 32 cpi r24, 0x25 ; 37 + 48e: 29 f4 brne .+10 ; 0x49a + 490: 90 e0 ldi r25, 0x00 ; 0 + 492: b3 01 movw r22, r6 + 494: 0e 94 21 04 call 0x842 ; 0x842 + 498: e4 cf rjmp .-56 ; 0x462 + 49a: ee 24 eor r14, r14 + 49c: dd 24 eor r13, r13 + 49e: 10 e0 ldi r17, 0x00 ; 0 + 4a0: 10 32 cpi r17, 0x20 ; 32 + 4a2: b0 f4 brcc .+44 ; 0x4d0 + 4a4: 8b 32 cpi r24, 0x2B ; 43 + 4a6: 69 f0 breq .+26 ; 0x4c2 + 4a8: 8c 32 cpi r24, 0x2C ; 44 + 4aa: 28 f4 brcc .+10 ; 0x4b6 + 4ac: 80 32 cpi r24, 0x20 ; 32 + 4ae: 51 f0 breq .+20 ; 0x4c4 + 4b0: 83 32 cpi r24, 0x23 ; 35 + 4b2: 71 f4 brne .+28 ; 0x4d0 + 4b4: 0b c0 rjmp .+22 ; 0x4cc + 4b6: 8d 32 cpi r24, 0x2D ; 45 + 4b8: 39 f0 breq .+14 ; 0x4c8 + 4ba: 80 33 cpi r24, 0x30 ; 48 + 4bc: 49 f4 brne .+18 ; 0x4d0 + 4be: 11 60 ori r17, 0x01 ; 1 + 4c0: 2c c0 rjmp .+88 ; 0x51a + 4c2: 12 60 ori r17, 0x02 ; 2 + 4c4: 14 60 ori r17, 0x04 ; 4 + 4c6: 29 c0 rjmp .+82 ; 0x51a + 4c8: 18 60 ori r17, 0x08 ; 8 + 4ca: 27 c0 rjmp .+78 ; 0x51a + 4cc: 10 61 ori r17, 0x10 ; 16 + 4ce: 25 c0 rjmp .+74 ; 0x51a + 4d0: 17 fd sbrc r17, 7 + 4d2: 2e c0 rjmp .+92 ; 0x530 + 4d4: 28 2f mov r18, r24 + 4d6: 20 53 subi r18, 0x30 ; 48 + 4d8: 2a 30 cpi r18, 0x0A ; 10 + 4da: 98 f4 brcc .+38 ; 0x502 + 4dc: 16 ff sbrs r17, 6 + 4de: 08 c0 rjmp .+16 ; 0x4f0 + 4e0: 8e 2d mov r24, r14 + 4e2: 88 0f add r24, r24 + 4e4: e8 2e mov r14, r24 + 4e6: ee 0c add r14, r14 + 4e8: ee 0c add r14, r14 + 4ea: e8 0e add r14, r24 + 4ec: e2 0e add r14, r18 + 4ee: 15 c0 rjmp .+42 ; 0x51a + 4f0: 8d 2d mov r24, r13 + 4f2: 88 0f add r24, r24 + 4f4: d8 2e mov r13, r24 + 4f6: dd 0c add r13, r13 + 4f8: dd 0c add r13, r13 + 4fa: d8 0e add r13, r24 + 4fc: d2 0e add r13, r18 + 4fe: 10 62 ori r17, 0x20 ; 32 + 500: 0c c0 rjmp .+24 ; 0x51a + 502: 8e 32 cpi r24, 0x2E ; 46 + 504: 21 f4 brne .+8 ; 0x50e + 506: 16 fd sbrc r17, 6 + 508: 6c c1 rjmp .+728 ; 0x7e2 + 50a: 10 64 ori r17, 0x40 ; 64 + 50c: 06 c0 rjmp .+12 ; 0x51a + 50e: 8c 36 cpi r24, 0x6C ; 108 + 510: 11 f4 brne .+4 ; 0x516 + 512: 10 68 ori r17, 0x80 ; 128 + 514: 02 c0 rjmp .+4 ; 0x51a + 516: 88 36 cpi r24, 0x68 ; 104 + 518: 59 f4 brne .+22 ; 0x530 + 51a: ec 85 ldd r30, Y+12 ; 0x0c + 51c: fd 85 ldd r31, Y+13 ; 0x0d + 51e: 93 fd sbrc r25, 3 + 520: 85 91 lpm r24, Z+ + 522: 93 ff sbrs r25, 3 + 524: 81 91 ld r24, Z+ + 526: fd 87 std Y+13, r31 ; 0x0d + 528: ec 87 std Y+12, r30 ; 0x0c + 52a: 88 23 and r24, r24 + 52c: 09 f0 breq .+2 ; 0x530 + 52e: b8 cf rjmp .-144 ; 0x4a0 + 530: 98 2f mov r25, r24 + 532: 95 54 subi r25, 0x45 ; 69 + 534: 93 30 cpi r25, 0x03 ; 3 + 536: 18 f0 brcs .+6 ; 0x53e + 538: 90 52 subi r25, 0x20 ; 32 + 53a: 93 30 cpi r25, 0x03 ; 3 + 53c: 30 f4 brcc .+12 ; 0x54a + 53e: 24 e0 ldi r18, 0x04 ; 4 + 540: 30 e0 ldi r19, 0x00 ; 0 + 542: a2 0e add r10, r18 + 544: b3 1e adc r11, r19 + 546: c9 82 std Y+1, r12 ; 0x01 + 548: 0f c0 rjmp .+30 ; 0x568 + 54a: 83 36 cpi r24, 0x63 ; 99 + 54c: 31 f0 breq .+12 ; 0x55a + 54e: 83 37 cpi r24, 0x73 ; 115 + 550: 81 f0 breq .+32 ; 0x572 + 552: 83 35 cpi r24, 0x53 ; 83 + 554: 09 f0 breq .+2 ; 0x558 + 556: 5a c0 rjmp .+180 ; 0x60c + 558: 22 c0 rjmp .+68 ; 0x59e + 55a: f5 01 movw r30, r10 + 55c: 80 81 ld r24, Z + 55e: 89 83 std Y+1, r24 ; 0x01 + 560: 22 e0 ldi r18, 0x02 ; 2 + 562: 30 e0 ldi r19, 0x00 ; 0 + 564: a2 0e add r10, r18 + 566: b3 1e adc r11, r19 + 568: 21 e0 ldi r18, 0x01 ; 1 + 56a: e2 2e mov r14, r18 + 56c: f1 2c mov r15, r1 + 56e: 42 01 movw r8, r4 + 570: 14 c0 rjmp .+40 ; 0x59a + 572: 92 e0 ldi r25, 0x02 ; 2 + 574: 29 2e mov r2, r25 + 576: 31 2c mov r3, r1 + 578: 2a 0c add r2, r10 + 57a: 3b 1c adc r3, r11 + 57c: f5 01 movw r30, r10 + 57e: 80 80 ld r8, Z + 580: 91 80 ldd r9, Z+1 ; 0x01 + 582: 16 ff sbrs r17, 6 + 584: 03 c0 rjmp .+6 ; 0x58c + 586: 6e 2d mov r22, r14 + 588: 70 e0 ldi r23, 0x00 ; 0 + 58a: 02 c0 rjmp .+4 ; 0x590 + 58c: 6f ef ldi r22, 0xFF ; 255 + 58e: 7f ef ldi r23, 0xFF ; 255 + 590: c4 01 movw r24, r8 + 592: 0e 94 06 04 call 0x80c ; 0x80c + 596: 7c 01 movw r14, r24 + 598: 51 01 movw r10, r2 + 59a: 1f 77 andi r17, 0x7F ; 127 + 59c: 15 c0 rjmp .+42 ; 0x5c8 + 59e: 82 e0 ldi r24, 0x02 ; 2 + 5a0: 28 2e mov r2, r24 + 5a2: 31 2c mov r3, r1 + 5a4: 2a 0c add r2, r10 + 5a6: 3b 1c adc r3, r11 + 5a8: f5 01 movw r30, r10 + 5aa: 80 80 ld r8, Z + 5ac: 91 80 ldd r9, Z+1 ; 0x01 + 5ae: 16 ff sbrs r17, 6 + 5b0: 03 c0 rjmp .+6 ; 0x5b8 + 5b2: 6e 2d mov r22, r14 + 5b4: 70 e0 ldi r23, 0x00 ; 0 + 5b6: 02 c0 rjmp .+4 ; 0x5bc + 5b8: 6f ef ldi r22, 0xFF ; 255 + 5ba: 7f ef ldi r23, 0xFF ; 255 + 5bc: c4 01 movw r24, r8 + 5be: 0e 94 fb 03 call 0x7f6 ; 0x7f6 + 5c2: 7c 01 movw r14, r24 + 5c4: 10 68 ori r17, 0x80 ; 128 + 5c6: 51 01 movw r10, r2 + 5c8: 13 fd sbrc r17, 3 + 5ca: 1c c0 rjmp .+56 ; 0x604 + 5cc: 06 c0 rjmp .+12 ; 0x5da + 5ce: 80 e2 ldi r24, 0x20 ; 32 + 5d0: 90 e0 ldi r25, 0x00 ; 0 + 5d2: b3 01 movw r22, r6 + 5d4: 0e 94 21 04 call 0x842 ; 0x842 + 5d8: da 94 dec r13 + 5da: 8d 2d mov r24, r13 + 5dc: 90 e0 ldi r25, 0x00 ; 0 + 5de: e8 16 cp r14, r24 + 5e0: f9 06 cpc r15, r25 + 5e2: a8 f3 brcs .-22 ; 0x5ce + 5e4: 0f c0 rjmp .+30 ; 0x604 + 5e6: f4 01 movw r30, r8 + 5e8: 17 fd sbrc r17, 7 + 5ea: 85 91 lpm r24, Z+ + 5ec: 17 ff sbrs r17, 7 + 5ee: 81 91 ld r24, Z+ + 5f0: 4f 01 movw r8, r30 + 5f2: 90 e0 ldi r25, 0x00 ; 0 + 5f4: b3 01 movw r22, r6 + 5f6: 0e 94 21 04 call 0x842 ; 0x842 + 5fa: d1 10 cpse r13, r1 + 5fc: da 94 dec r13 + 5fe: 08 94 sec + 600: e1 08 sbc r14, r1 + 602: f1 08 sbc r15, r1 + 604: e1 14 cp r14, r1 + 606: f1 04 cpc r15, r1 + 608: 71 f7 brne .-36 ; 0x5e6 + 60a: e8 c0 rjmp .+464 ; 0x7dc + 60c: 84 36 cpi r24, 0x64 ; 100 + 60e: 11 f0 breq .+4 ; 0x614 + 610: 89 36 cpi r24, 0x69 ; 105 + 612: 59 f5 brne .+86 ; 0x66a + 614: f5 01 movw r30, r10 + 616: 17 ff sbrs r17, 7 + 618: 07 c0 rjmp .+14 ; 0x628 + 61a: 80 81 ld r24, Z + 61c: 91 81 ldd r25, Z+1 ; 0x01 + 61e: a2 81 ldd r26, Z+2 ; 0x02 + 620: b3 81 ldd r27, Z+3 ; 0x03 + 622: 24 e0 ldi r18, 0x04 ; 4 + 624: 30 e0 ldi r19, 0x00 ; 0 + 626: 09 c0 rjmp .+18 ; 0x63a + 628: 60 81 ld r22, Z + 62a: 71 81 ldd r23, Z+1 ; 0x01 + 62c: cb 01 movw r24, r22 + 62e: aa 27 eor r26, r26 + 630: 97 fd sbrc r25, 7 + 632: a0 95 com r26 + 634: ba 2f mov r27, r26 + 636: 22 e0 ldi r18, 0x02 ; 2 + 638: 30 e0 ldi r19, 0x00 ; 0 + 63a: a2 0e add r10, r18 + 63c: b3 1e adc r11, r19 + 63e: 01 2f mov r16, r17 + 640: 0f 76 andi r16, 0x6F ; 111 + 642: b7 ff sbrs r27, 7 + 644: 08 c0 rjmp .+16 ; 0x656 + 646: b0 95 com r27 + 648: a0 95 com r26 + 64a: 90 95 com r25 + 64c: 81 95 neg r24 + 64e: 9f 4f sbci r25, 0xFF ; 255 + 650: af 4f sbci r26, 0xFF ; 255 + 652: bf 4f sbci r27, 0xFF ; 255 + 654: 00 68 ori r16, 0x80 ; 128 + 656: bc 01 movw r22, r24 + 658: cd 01 movw r24, r26 + 65a: a2 01 movw r20, r4 + 65c: 2a e0 ldi r18, 0x0A ; 10 + 65e: 30 e0 ldi r19, 0x00 ; 0 + 660: 0e 94 4d 04 call 0x89a ; 0x89a <__ultoa_invert> + 664: f8 2e mov r15, r24 + 666: f4 18 sub r15, r4 + 668: 3f c0 rjmp .+126 ; 0x6e8 + 66a: 85 37 cpi r24, 0x75 ; 117 + 66c: 21 f4 brne .+8 ; 0x676 + 66e: 1f 7e andi r17, 0xEF ; 239 + 670: 2a e0 ldi r18, 0x0A ; 10 + 672: 30 e0 ldi r19, 0x00 ; 0 + 674: 20 c0 rjmp .+64 ; 0x6b6 + 676: 19 7f andi r17, 0xF9 ; 249 + 678: 8f 36 cpi r24, 0x6F ; 111 + 67a: a9 f0 breq .+42 ; 0x6a6 + 67c: 80 37 cpi r24, 0x70 ; 112 + 67e: 20 f4 brcc .+8 ; 0x688 + 680: 88 35 cpi r24, 0x58 ; 88 + 682: 09 f0 breq .+2 ; 0x686 + 684: ae c0 rjmp .+348 ; 0x7e2 + 686: 0b c0 rjmp .+22 ; 0x69e + 688: 80 37 cpi r24, 0x70 ; 112 + 68a: 21 f0 breq .+8 ; 0x694 + 68c: 88 37 cpi r24, 0x78 ; 120 + 68e: 09 f0 breq .+2 ; 0x692 + 690: a8 c0 rjmp .+336 ; 0x7e2 + 692: 01 c0 rjmp .+2 ; 0x696 + 694: 10 61 ori r17, 0x10 ; 16 + 696: 14 ff sbrs r17, 4 + 698: 09 c0 rjmp .+18 ; 0x6ac + 69a: 14 60 ori r17, 0x04 ; 4 + 69c: 07 c0 rjmp .+14 ; 0x6ac + 69e: 14 ff sbrs r17, 4 + 6a0: 08 c0 rjmp .+16 ; 0x6b2 + 6a2: 16 60 ori r17, 0x06 ; 6 + 6a4: 06 c0 rjmp .+12 ; 0x6b2 + 6a6: 28 e0 ldi r18, 0x08 ; 8 + 6a8: 30 e0 ldi r19, 0x00 ; 0 + 6aa: 05 c0 rjmp .+10 ; 0x6b6 + 6ac: 20 e1 ldi r18, 0x10 ; 16 + 6ae: 30 e0 ldi r19, 0x00 ; 0 + 6b0: 02 c0 rjmp .+4 ; 0x6b6 + 6b2: 20 e1 ldi r18, 0x10 ; 16 + 6b4: 32 e0 ldi r19, 0x02 ; 2 + 6b6: f5 01 movw r30, r10 + 6b8: 17 ff sbrs r17, 7 + 6ba: 07 c0 rjmp .+14 ; 0x6ca + 6bc: 60 81 ld r22, Z + 6be: 71 81 ldd r23, Z+1 ; 0x01 + 6c0: 82 81 ldd r24, Z+2 ; 0x02 + 6c2: 93 81 ldd r25, Z+3 ; 0x03 + 6c4: 44 e0 ldi r20, 0x04 ; 4 + 6c6: 50 e0 ldi r21, 0x00 ; 0 + 6c8: 06 c0 rjmp .+12 ; 0x6d6 + 6ca: 60 81 ld r22, Z + 6cc: 71 81 ldd r23, Z+1 ; 0x01 + 6ce: 80 e0 ldi r24, 0x00 ; 0 + 6d0: 90 e0 ldi r25, 0x00 ; 0 + 6d2: 42 e0 ldi r20, 0x02 ; 2 + 6d4: 50 e0 ldi r21, 0x00 ; 0 + 6d6: a4 0e add r10, r20 + 6d8: b5 1e adc r11, r21 + 6da: a2 01 movw r20, r4 + 6dc: 0e 94 4d 04 call 0x89a ; 0x89a <__ultoa_invert> + 6e0: f8 2e mov r15, r24 + 6e2: f4 18 sub r15, r4 + 6e4: 01 2f mov r16, r17 + 6e6: 0f 77 andi r16, 0x7F ; 127 + 6e8: 06 ff sbrs r16, 6 + 6ea: 09 c0 rjmp .+18 ; 0x6fe + 6ec: 0e 7f andi r16, 0xFE ; 254 + 6ee: fe 14 cp r15, r14 + 6f0: 30 f4 brcc .+12 ; 0x6fe + 6f2: 04 ff sbrs r16, 4 + 6f4: 06 c0 rjmp .+12 ; 0x702 + 6f6: 02 fd sbrc r16, 2 + 6f8: 04 c0 rjmp .+8 ; 0x702 + 6fa: 0f 7e andi r16, 0xEF ; 239 + 6fc: 02 c0 rjmp .+4 ; 0x702 + 6fe: 1f 2d mov r17, r15 + 700: 01 c0 rjmp .+2 ; 0x704 + 702: 1e 2d mov r17, r14 + 704: 80 2f mov r24, r16 + 706: 90 e0 ldi r25, 0x00 ; 0 + 708: 04 ff sbrs r16, 4 + 70a: 0c c0 rjmp .+24 ; 0x724 + 70c: fe 01 movw r30, r28 + 70e: ef 0d add r30, r15 + 710: f1 1d adc r31, r1 + 712: 20 81 ld r18, Z + 714: 20 33 cpi r18, 0x30 ; 48 + 716: 11 f4 brne .+4 ; 0x71c + 718: 09 7e andi r16, 0xE9 ; 233 + 71a: 09 c0 rjmp .+18 ; 0x72e + 71c: 02 ff sbrs r16, 2 + 71e: 06 c0 rjmp .+12 ; 0x72c + 720: 1e 5f subi r17, 0xFE ; 254 + 722: 05 c0 rjmp .+10 ; 0x72e + 724: 86 78 andi r24, 0x86 ; 134 + 726: 90 70 andi r25, 0x00 ; 0 + 728: 00 97 sbiw r24, 0x00 ; 0 + 72a: 09 f0 breq .+2 ; 0x72e + 72c: 1f 5f subi r17, 0xFF ; 255 + 72e: 80 2e mov r8, r16 + 730: 99 24 eor r9, r9 + 732: 03 fd sbrc r16, 3 + 734: 12 c0 rjmp .+36 ; 0x75a + 736: 00 ff sbrs r16, 0 + 738: 0d c0 rjmp .+26 ; 0x754 + 73a: ef 2c mov r14, r15 + 73c: 1d 15 cp r17, r13 + 73e: 50 f4 brcc .+20 ; 0x754 + 740: ed 0c add r14, r13 + 742: e1 1a sub r14, r17 + 744: 1d 2d mov r17, r13 + 746: 06 c0 rjmp .+12 ; 0x754 + 748: 80 e2 ldi r24, 0x20 ; 32 + 74a: 90 e0 ldi r25, 0x00 ; 0 + 74c: b3 01 movw r22, r6 + 74e: 0e 94 21 04 call 0x842 ; 0x842 + 752: 1f 5f subi r17, 0xFF ; 255 + 754: 1d 15 cp r17, r13 + 756: c0 f3 brcs .-16 ; 0x748 + 758: 04 c0 rjmp .+8 ; 0x762 + 75a: 1d 15 cp r17, r13 + 75c: 10 f4 brcc .+4 ; 0x762 + 75e: d1 1a sub r13, r17 + 760: 01 c0 rjmp .+2 ; 0x764 + 762: dd 24 eor r13, r13 + 764: 84 fe sbrs r8, 4 + 766: 0f c0 rjmp .+30 ; 0x786 + 768: 80 e3 ldi r24, 0x30 ; 48 + 76a: 90 e0 ldi r25, 0x00 ; 0 + 76c: b3 01 movw r22, r6 + 76e: 0e 94 21 04 call 0x842 ; 0x842 + 772: 82 fe sbrs r8, 2 + 774: 1f c0 rjmp .+62 ; 0x7b4 + 776: 81 fe sbrs r8, 1 + 778: 03 c0 rjmp .+6 ; 0x780 + 77a: 88 e5 ldi r24, 0x58 ; 88 + 77c: 90 e0 ldi r25, 0x00 ; 0 + 77e: 10 c0 rjmp .+32 ; 0x7a0 + 780: 88 e7 ldi r24, 0x78 ; 120 + 782: 90 e0 ldi r25, 0x00 ; 0 + 784: 0d c0 rjmp .+26 ; 0x7a0 + 786: c4 01 movw r24, r8 + 788: 86 78 andi r24, 0x86 ; 134 + 78a: 90 70 andi r25, 0x00 ; 0 + 78c: 00 97 sbiw r24, 0x00 ; 0 + 78e: 91 f0 breq .+36 ; 0x7b4 + 790: 81 fc sbrc r8, 1 + 792: 02 c0 rjmp .+4 ; 0x798 + 794: 80 e2 ldi r24, 0x20 ; 32 + 796: 01 c0 rjmp .+2 ; 0x79a + 798: 8b e2 ldi r24, 0x2B ; 43 + 79a: 07 fd sbrc r16, 7 + 79c: 8d e2 ldi r24, 0x2D ; 45 + 79e: 90 e0 ldi r25, 0x00 ; 0 + 7a0: b3 01 movw r22, r6 + 7a2: 0e 94 21 04 call 0x842 ; 0x842 + 7a6: 06 c0 rjmp .+12 ; 0x7b4 + 7a8: 80 e3 ldi r24, 0x30 ; 48 + 7aa: 90 e0 ldi r25, 0x00 ; 0 + 7ac: b3 01 movw r22, r6 + 7ae: 0e 94 21 04 call 0x842 ; 0x842 + 7b2: ea 94 dec r14 + 7b4: fe 14 cp r15, r14 + 7b6: c0 f3 brcs .-16 ; 0x7a8 + 7b8: fa 94 dec r15 + 7ba: f2 01 movw r30, r4 + 7bc: ef 0d add r30, r15 + 7be: f1 1d adc r31, r1 + 7c0: 80 81 ld r24, Z + 7c2: 90 e0 ldi r25, 0x00 ; 0 + 7c4: b3 01 movw r22, r6 + 7c6: 0e 94 21 04 call 0x842 ; 0x842 + 7ca: ff 20 and r15, r15 + 7cc: a9 f7 brne .-22 ; 0x7b8 + 7ce: 06 c0 rjmp .+12 ; 0x7dc + 7d0: 80 e2 ldi r24, 0x20 ; 32 + 7d2: 90 e0 ldi r25, 0x00 ; 0 + 7d4: b3 01 movw r22, r6 + 7d6: 0e 94 21 04 call 0x842 ; 0x842 + 7da: da 94 dec r13 + 7dc: dd 20 and r13, r13 + 7de: c1 f7 brne .-16 ; 0x7d0 + 7e0: 40 ce rjmp .-896 ; 0x462 + 7e2: f3 01 movw r30, r6 + 7e4: 86 81 ldd r24, Z+6 ; 0x06 + 7e6: 97 81 ldd r25, Z+7 ; 0x07 + 7e8: 02 c0 rjmp .+4 ; 0x7ee + 7ea: 8f ef ldi r24, 0xFF ; 255 + 7ec: 9f ef ldi r25, 0xFF ; 255 + 7ee: 2d 96 adiw r28, 0x0d ; 13 + 7f0: e2 e1 ldi r30, 0x12 ; 18 + 7f2: 0c 94 c7 04 jmp 0x98e ; 0x98e <__epilogue_restores__> + +000007f6 : + 7f6: fc 01 movw r30, r24 + 7f8: 05 90 lpm r0, Z+ + 7fa: 61 50 subi r22, 0x01 ; 1 + 7fc: 70 40 sbci r23, 0x00 ; 0 + 7fe: 01 10 cpse r0, r1 + 800: d8 f7 brcc .-10 ; 0x7f8 + 802: 80 95 com r24 + 804: 90 95 com r25 + 806: 8e 0f add r24, r30 + 808: 9f 1f adc r25, r31 + 80a: 08 95 ret + +0000080c : + 80c: fc 01 movw r30, r24 + 80e: 61 50 subi r22, 0x01 ; 1 + 810: 70 40 sbci r23, 0x00 ; 0 + 812: 01 90 ld r0, Z+ + 814: 01 10 cpse r0, r1 + 816: d8 f7 brcc .-10 ; 0x80e + 818: 80 95 com r24 + 81a: 90 95 com r25 + 81c: 8e 0f add r24, r30 + 81e: 9f 1f adc r25, r31 + 820: 08 95 ret + +00000822 : + 822: dc 01 movw r26, r24 + 824: fc 01 movw r30, r24 + 826: 67 2f mov r22, r23 + 828: 71 91 ld r23, Z+ + 82a: 77 23 and r23, r23 + 82c: e1 f7 brne .-8 ; 0x826 + 82e: 32 97 sbiw r30, 0x02 ; 2 + 830: 04 c0 rjmp .+8 ; 0x83a + 832: 7c 91 ld r23, X + 834: 6d 93 st X+, r22 + 836: 70 83 st Z, r23 + 838: 62 91 ld r22, -Z + 83a: ae 17 cp r26, r30 + 83c: bf 07 cpc r27, r31 + 83e: c8 f3 brcs .-14 ; 0x832 + 840: 08 95 ret + +00000842 : + 842: 0f 93 push r16 + 844: 1f 93 push r17 + 846: cf 93 push r28 + 848: df 93 push r29 + 84a: 8c 01 movw r16, r24 + 84c: eb 01 movw r28, r22 + 84e: 8b 81 ldd r24, Y+3 ; 0x03 + 850: 81 ff sbrs r24, 1 + 852: 1b c0 rjmp .+54 ; 0x88a + 854: 82 ff sbrs r24, 2 + 856: 0d c0 rjmp .+26 ; 0x872 + 858: 2e 81 ldd r18, Y+6 ; 0x06 + 85a: 3f 81 ldd r19, Y+7 ; 0x07 + 85c: 8c 81 ldd r24, Y+4 ; 0x04 + 85e: 9d 81 ldd r25, Y+5 ; 0x05 + 860: 28 17 cp r18, r24 + 862: 39 07 cpc r19, r25 + 864: 64 f4 brge .+24 ; 0x87e + 866: e8 81 ld r30, Y + 868: f9 81 ldd r31, Y+1 ; 0x01 + 86a: 01 93 st Z+, r16 + 86c: f9 83 std Y+1, r31 ; 0x01 + 86e: e8 83 st Y, r30 + 870: 06 c0 rjmp .+12 ; 0x87e + 872: e8 85 ldd r30, Y+8 ; 0x08 + 874: f9 85 ldd r31, Y+9 ; 0x09 + 876: 80 2f mov r24, r16 + 878: 09 95 icall + 87a: 00 97 sbiw r24, 0x00 ; 0 + 87c: 31 f4 brne .+12 ; 0x88a + 87e: 8e 81 ldd r24, Y+6 ; 0x06 + 880: 9f 81 ldd r25, Y+7 ; 0x07 + 882: 01 96 adiw r24, 0x01 ; 1 + 884: 9f 83 std Y+7, r25 ; 0x07 + 886: 8e 83 std Y+6, r24 ; 0x06 + 888: 02 c0 rjmp .+4 ; 0x88e + 88a: 0f ef ldi r16, 0xFF ; 255 + 88c: 1f ef ldi r17, 0xFF ; 255 + 88e: c8 01 movw r24, r16 + 890: df 91 pop r29 + 892: cf 91 pop r28 + 894: 1f 91 pop r17 + 896: 0f 91 pop r16 + 898: 08 95 ret + +0000089a <__ultoa_invert>: + 89a: fa 01 movw r30, r20 + 89c: aa 27 eor r26, r26 + 89e: 28 30 cpi r18, 0x08 ; 8 + 8a0: 51 f1 breq .+84 ; 0x8f6 <__ultoa_invert+0x5c> + 8a2: 20 31 cpi r18, 0x10 ; 16 + 8a4: 81 f1 breq .+96 ; 0x906 <__stack+0x7> + 8a6: e8 94 clt + 8a8: 6f 93 push r22 + 8aa: 6e 7f andi r22, 0xFE ; 254 + 8ac: 6e 5f subi r22, 0xFE ; 254 + 8ae: 7f 4f sbci r23, 0xFF ; 255 + 8b0: 8f 4f sbci r24, 0xFF ; 255 + 8b2: 9f 4f sbci r25, 0xFF ; 255 + 8b4: af 4f sbci r26, 0xFF ; 255 + 8b6: b1 e0 ldi r27, 0x01 ; 1 + 8b8: 3e d0 rcall .+124 ; 0x936 <__stack+0x37> + 8ba: b4 e0 ldi r27, 0x04 ; 4 + 8bc: 3c d0 rcall .+120 ; 0x936 <__stack+0x37> + 8be: 67 0f add r22, r23 + 8c0: 78 1f adc r23, r24 + 8c2: 89 1f adc r24, r25 + 8c4: 9a 1f adc r25, r26 + 8c6: a1 1d adc r26, r1 + 8c8: 68 0f add r22, r24 + 8ca: 79 1f adc r23, r25 + 8cc: 8a 1f adc r24, r26 + 8ce: 91 1d adc r25, r1 + 8d0: a1 1d adc r26, r1 + 8d2: 6a 0f add r22, r26 + 8d4: 71 1d adc r23, r1 + 8d6: 81 1d adc r24, r1 + 8d8: 91 1d adc r25, r1 + 8da: a1 1d adc r26, r1 + 8dc: 20 d0 rcall .+64 ; 0x91e <__stack+0x1f> + 8de: 09 f4 brne .+2 ; 0x8e2 <__ultoa_invert+0x48> + 8e0: 68 94 set + 8e2: 3f 91 pop r19 + 8e4: 2a e0 ldi r18, 0x0A ; 10 + 8e6: 26 9f mul r18, r22 + 8e8: 11 24 eor r1, r1 + 8ea: 30 19 sub r19, r0 + 8ec: 30 5d subi r19, 0xD0 ; 208 + 8ee: 31 93 st Z+, r19 + 8f0: de f6 brtc .-74 ; 0x8a8 <__ultoa_invert+0xe> + 8f2: cf 01 movw r24, r30 + 8f4: 08 95 ret + 8f6: 46 2f mov r20, r22 + 8f8: 47 70 andi r20, 0x07 ; 7 + 8fa: 40 5d subi r20, 0xD0 ; 208 + 8fc: 41 93 st Z+, r20 + 8fe: b3 e0 ldi r27, 0x03 ; 3 + 900: 0f d0 rcall .+30 ; 0x920 <__stack+0x21> + 902: c9 f7 brne .-14 ; 0x8f6 <__ultoa_invert+0x5c> + 904: f6 cf rjmp .-20 ; 0x8f2 <__ultoa_invert+0x58> + 906: 46 2f mov r20, r22 + 908: 4f 70 andi r20, 0x0F ; 15 + 90a: 40 5d subi r20, 0xD0 ; 208 + 90c: 4a 33 cpi r20, 0x3A ; 58 + 90e: 18 f0 brcs .+6 ; 0x916 <__stack+0x17> + 910: 49 5d subi r20, 0xD9 ; 217 + 912: 31 fd sbrc r19, 1 + 914: 40 52 subi r20, 0x20 ; 32 + 916: 41 93 st Z+, r20 + 918: 02 d0 rcall .+4 ; 0x91e <__stack+0x1f> + 91a: a9 f7 brne .-22 ; 0x906 <__stack+0x7> + 91c: ea cf rjmp .-44 ; 0x8f2 <__ultoa_invert+0x58> + 91e: b4 e0 ldi r27, 0x04 ; 4 + 920: a6 95 lsr r26 + 922: 97 95 ror r25 + 924: 87 95 ror r24 + 926: 77 95 ror r23 + 928: 67 95 ror r22 + 92a: ba 95 dec r27 + 92c: c9 f7 brne .-14 ; 0x920 <__stack+0x21> + 92e: 00 97 sbiw r24, 0x00 ; 0 + 930: 61 05 cpc r22, r1 + 932: 71 05 cpc r23, r1 + 934: 08 95 ret + 936: 9b 01 movw r18, r22 + 938: ac 01 movw r20, r24 + 93a: 0a 2e mov r0, r26 + 93c: 06 94 lsr r0 + 93e: 57 95 ror r21 + 940: 47 95 ror r20 + 942: 37 95 ror r19 + 944: 27 95 ror r18 + 946: ba 95 dec r27 + 948: c9 f7 brne .-14 ; 0x93c <__stack+0x3d> + 94a: 62 0f add r22, r18 + 94c: 73 1f adc r23, r19 + 94e: 84 1f adc r24, r20 + 950: 95 1f adc r25, r21 + 952: a0 1d adc r26, r0 + 954: 08 95 ret + +00000956 <__prologue_saves__>: + 956: 2f 92 push r2 + 958: 3f 92 push r3 + 95a: 4f 92 push r4 + 95c: 5f 92 push r5 + 95e: 6f 92 push r6 + 960: 7f 92 push r7 + 962: 8f 92 push r8 + 964: 9f 92 push r9 + 966: af 92 push r10 + 968: bf 92 push r11 + 96a: cf 92 push r12 + 96c: df 92 push r13 + 96e: ef 92 push r14 + 970: ff 92 push r15 + 972: 0f 93 push r16 + 974: 1f 93 push r17 + 976: cf 93 push r28 + 978: df 93 push r29 + 97a: cd b7 in r28, 0x3d ; 61 + 97c: de b7 in r29, 0x3e ; 62 + 97e: ca 1b sub r28, r26 + 980: db 0b sbc r29, r27 + 982: 0f b6 in r0, 0x3f ; 63 + 984: f8 94 cli + 986: de bf out 0x3e, r29 ; 62 + 988: 0f be out 0x3f, r0 ; 63 + 98a: cd bf out 0x3d, r28 ; 61 + 98c: 09 94 ijmp + +0000098e <__epilogue_restores__>: + 98e: 2a 88 ldd r2, Y+18 ; 0x12 + 990: 39 88 ldd r3, Y+17 ; 0x11 + 992: 48 88 ldd r4, Y+16 ; 0x10 + 994: 5f 84 ldd r5, Y+15 ; 0x0f + 996: 6e 84 ldd r6, Y+14 ; 0x0e + 998: 7d 84 ldd r7, Y+13 ; 0x0d + 99a: 8c 84 ldd r8, Y+12 ; 0x0c + 99c: 9b 84 ldd r9, Y+11 ; 0x0b + 99e: aa 84 ldd r10, Y+10 ; 0x0a + 9a0: b9 84 ldd r11, Y+9 ; 0x09 + 9a2: c8 84 ldd r12, Y+8 ; 0x08 + 9a4: df 80 ldd r13, Y+7 ; 0x07 + 9a6: ee 80 ldd r14, Y+6 ; 0x06 + 9a8: fd 80 ldd r15, Y+5 ; 0x05 + 9aa: 0c 81 ldd r16, Y+4 ; 0x04 + 9ac: 1b 81 ldd r17, Y+3 ; 0x03 + 9ae: aa 81 ldd r26, Y+2 ; 0x02 + 9b0: b9 81 ldd r27, Y+1 ; 0x01 + 9b2: ce 0f add r28, r30 + 9b4: d1 1d adc r29, r1 + 9b6: 0f b6 in r0, 0x3f ; 63 + 9b8: f8 94 cli + 9ba: de bf out 0x3e, r29 ; 62 + 9bc: 0f be out 0x3f, r0 ; 63 + 9be: cd bf out 0x3d, r28 ; 61 + 9c0: ed 01 movw r28, r26 + 9c2: 08 95 ret + +000009c4 <_exit>: + 9c4: f8 94 cli + +000009c6 <__stop_program>: + 9c6: ff cf rjmp .-2 ; 0x9c6 <__stop_program> diff --git a/tpic6b595_shiftout/main.lst b/tpic6b595_shiftout/main.lst new file mode 100644 index 0000000..b76ef57 --- /dev/null +++ b/tpic6b595_shiftout/main.lst @@ -0,0 +1,673 @@ + 1 .file "main.c" + 2 __SREG__ = 0x3f + 3 __SP_H__ = 0x3e + 4 __SP_L__ = 0x3d + 5 __tmp_reg__ = 0 + 6 __zero_reg__ = 1 + 7 .global __do_copy_data + 8 .global __do_clear_bss + 9 .text + 10 .Ltext0: + 11 .global shift_out + 13 shift_out: + 14 .LFB6: + 15 .file 1 "main.c" + 1:main.c **** /* + 2:main.c **** * Code to write data to TPIC6B595 SIPO shift register. + 3:main.c **** * + 4:main.c **** * The TPIC6B595 is a monolithic, high-voltage, medium-current power 8-bit + 5:main.c **** * shift register designed for use in systems that require relatively high + 6:main.c **** * load power. + 7:main.c **** * + 8:main.c **** * This device contains an 8-bit serial-in, parallel-out shift register that + 9:main.c **** * feeds an 8-bit D-type storage register. Data transfers through both the + 10:main.c **** * shift and storage registers on the rising edge of the shift-register clock + 11:main.c **** * (SRCK) and the register clock (RCK), respectively. The storage register + 12:main.c **** * transfers data to the output buffer when shift-register clear (SRCLR) is + 13:main.c **** * high. When SRCLR is low, the input shift register is cleared. When output + 14:main.c **** * enable (G) is held high, all data in the output buffers is held low and all + 15:main.c **** * drain outputs are off. When G is held low, data from the storage register + 16:main.c **** * is transparent to the output buffers. When data in the output buffers is + 17:main.c **** * low, the DMOS-transistor outputs are off. When data is high, the DMOS- + 18:main.c **** * transistor outputs have sink-current capability. The serial output (SER + 19:main.c **** * OUT) allows for cascading of the data from the shift register to additional + 20:main.c **** * devices. + 21:main.c **** * + 22:main.c **** * http://www.adafruit.com/datasheets/tpic6b595.pdf + 23:main.c **** * + 24:main.c **** * To compile and upload run: make clean; make; make program; + 25:main.c **** * + 26:main.c **** * Copyright 2011 Mika Tuupola + 27:main.c **** * + 28:main.c **** * Licensed under the MIT license: + 29:main.c **** * http://www.opensource.org/licenses/mit-license.php + 30:main.c **** * + 31:main.c **** */ + 32:main.c **** + 33:main.c **** #include + 34:main.c **** #include + 35:main.c **** #include + 36:main.c **** + 37:main.c **** #include "main.h" + 38:main.c **** #include "uart.h" + 39:main.c **** #include "pins.h" + 40:main.c **** #include "digital.h" + 41:main.c **** + 42:main.c **** #define LATCH 10 /* RCK */ + 43:main.c **** #define DATA 11 /* SER IN */ + 44:main.c **** #define CLOCK 13 /* SRCK */ + 45:main.c **** + 46:main.c **** static void init(void) { + 47:main.c **** pin_mode(LATCH, OUTPUT); + 48:main.c **** pin_mode(CLOCK, OUTPUT); + 49:main.c **** pin_mode(DATA, OUTPUT); + 50:main.c **** } + 51:main.c **** + 52:main.c **** /* Assumes MSB first. */ + 53:main.c **** void shift_out(uint8_t data) { + 16 .loc 1 53 0 + 17 .LVL0: + 18 /* prologue: function */ + 19 /* frame size = 0 */ + 20 /* stack size = 0 */ + 21 .L__stack_usage = 0 + 22 .loc 1 53 0 + 23 0000 27E0 ldi r18,lo8(7) + 24 0002 30E0 ldi r19,hi8(7) + 25 .LBB21: + 54:main.c **** for(uint8_t i = 0; i < 8; i++) { + 55:main.c **** /* Write bit to data port. */ + 56:main.c **** if (0 == (data & _BV(7 - i))) { + 26 .loc 1 56 0 + 27 0004 90E0 ldi r25,lo8(0) + 28 .LVL1: + 29 .L4: + 30 0006 AC01 movw r20,r24 + 31 0008 022E mov r0,r18 + 32 000a 00C0 rjmp 2f + 33 000c 5595 1: asr r21 + 34 000e 4795 ror r20 + 35 0010 0A94 2: dec r0 + 36 0012 02F4 brpl 1b + 37 0014 40FD sbrc r20,0 + 38 0016 00C0 rjmp .L2 + 57:main.c **** digital_write(DATA, LOW); + 39 .loc 1 57 0 + 40 0018 2B98 cbi 37-0x20,3 + 41 001a 00C0 rjmp .L3 + 42 .L2: + 58:main.c **** } else { + 59:main.c **** digital_write(DATA, HIGH); + 43 .loc 1 59 0 + 44 001c 2B9A sbi 37-0x20,3 + 45 .L3: + 60:main.c **** } + 61:main.c **** + 62:main.c **** /* Pulse clock input to write next bit. */ + 63:main.c **** digital_write(CLOCK, LOW); + 46 .loc 1 63 0 + 47 001e 2D98 cbi 37-0x20,5 + 64:main.c **** digital_write(CLOCK, HIGH); + 48 .loc 1 64 0 + 49 0020 2D9A sbi 37-0x20,5 + 50 0022 2150 subi r18,lo8(-(-1)) + 51 0024 3040 sbci r19,hi8(-(-1)) + 54:main.c **** for(uint8_t i = 0; i < 8; i++) { + 52 .loc 1 54 0 + 53 0026 4FEF ldi r20,hi8(-1) + 54 0028 2F3F cpi r18,lo8(-1) + 55 002a 3407 cpc r19,r20 + 56 002c 01F4 brne .L4 + 57 /* epilogue start */ + 58 .LBE21: + 65:main.c **** } + 66:main.c **** } + 59 .loc 1 66 0 + 60 002e 0895 ret + 61 .LFE6: + 63 .data + 64 .LC0: + 65 0000 2573 2025 .string "%s %d \n" + 65 6420 0A00 + 66 .section .text.startup,"ax",@progbits + 67 .global main + 69 main: + 70 .LFB7: + 67:main.c **** + 68:main.c **** int main(void) { + 71 .loc 1 68 0 + 72 0000 CF93 push r28 + 73 .LCFI0: + 74 0002 DF93 push r29 + 75 .LCFI1: + 76 0004 CDB7 in r28,__SP_L__ + 77 0006 DEB7 in r29,__SP_H__ + 78 0008 6197 sbiw r28,17 + 79 .LCFI2: + 80 000a 0FB6 in __tmp_reg__,__SREG__ + 81 000c F894 cli + 82 000e DEBF out __SP_H__,r29 + 83 0010 0FBE out __SREG__,__tmp_reg__ + 84 0012 CDBF out __SP_L__,r28 + 85 /* prologue: function */ + 86 /* frame size = 17 */ + 87 /* stack size = 19 */ + 88 .L__stack_usage = 19 + 89 .LBB22: + 90 .LBB23: + 47:main.c **** pin_mode(LATCH, OUTPUT); + 91 .loc 1 47 0 + 92 0014 229A sbi 36-0x20,2 + 48:main.c **** pin_mode(CLOCK, OUTPUT); + 93 .loc 1 48 0 + 94 0016 259A sbi 36-0x20,5 + 49:main.c **** pin_mode(DATA, OUTPUT); + 95 .loc 1 49 0 + 96 0018 239A sbi 36-0x20,3 + 97 .LBE23: + 98 .LBE22: + 69:main.c **** + 70:main.c **** init(); + 71:main.c **** uart_init(); + 99 .loc 1 71 0 + 100 001a 0E94 0000 call uart_init + 72:main.c **** stdout = &uart_output; + 101 .loc 1 72 0 + 102 001e 80E0 ldi r24,lo8(uart_output) + 103 0020 90E0 ldi r25,hi8(uart_output) + 104 0022 9093 0000 sts __iob+2+1,r25 + 105 0026 8093 0000 sts __iob+2,r24 + 73:main.c **** stdin = &uart_input; + 106 .loc 1 73 0 + 107 002a 80E0 ldi r24,lo8(uart_input) + 108 002c 90E0 ldi r25,hi8(uart_input) + 109 002e 9093 0000 sts __iob+1,r25 + 110 0032 8093 0000 sts __iob,r24 + 74:main.c **** + 75:main.c **** char binary[17]; + 76:main.c **** + 77:main.c **** /* Show pattern for 5 seconds. */ + 78:main.c **** shift_out(0b10101010); + 111 .loc 1 78 0 + 112 0036 8AEA ldi r24,lo8(-86) + 113 0038 0E94 0000 call shift_out + 79:main.c **** shift_out(0b11110000); + 114 .loc 1 79 0 + 115 003c 80EF ldi r24,lo8(-16) + 116 003e 0E94 0000 call shift_out + 80:main.c **** digital_write(LATCH, LOW); + 117 .loc 1 80 0 + 118 0042 2A98 cbi 37-0x20,2 + 81:main.c **** digital_write(LATCH, HIGH); + 119 .loc 1 81 0 + 120 0044 2A9A sbi 37-0x20,2 + 121 .LVL2: + 122 0046 80E5 ldi r24,lo8(-15536) + 123 0048 93EC ldi r25,hi8(-15536) + 124 .LBB24: + 125 .LBB25: + 126 .LBB26: + 127 .LBB27: + 128 .file 2 "/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basi + 1:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** /* Copyright (c) 2002, Marek Michalkiewicz + 2:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** Copyright (c) 2007 Joerg Wunsch + 3:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** All rights reserved. + 4:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** + 5:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** Redistribution and use in source and binary forms, with or without + 6:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** modification, are permitted provided that the following conditions are met: + 7:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** + 8:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** * Redistributions of source code must retain the above copyright + 9:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** notice, this list of conditions and the following disclaimer. + 10:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** + 11:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** * Redistributions in binary form must reproduce the above copyright + 12:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** notice, this list of conditions and the following disclaimer in + 13:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** the documentation and/or other materials provided with the + 14:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** distribution. + 15:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** + 16:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** * Neither the name of the copyright holders nor the names of + 17:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** contributors may be used to endorse or promote products derived + 18:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** from this software without specific prior written permission. + 19:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** + 20:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 21:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 22:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + 23:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + 24:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + 25:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + 26:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + 27:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + 28:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + 29:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + 30:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** POSSIBILITY OF SUCH DAMAGE. */ + 31:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** + 32:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** /* $Id: delay_basic.h 2143 2010-06-08 21:19:51Z joerg_wunsch $ */ + 33:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** + 34:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** #ifndef _UTIL_DELAY_BASIC_H_ + 35:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** #define _UTIL_DELAY_BASIC_H_ 1 + 36:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** + 37:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** #include + 38:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** + 39:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** #if !defined(__DOXYGEN__) + 40:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** static inline void _delay_loop_1(uint8_t __count) __attribute__((always_inline)); + 41:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** static inline void _delay_loop_2(uint16_t __count) __attribute__((always_inline)); + 42:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** #endif + 43:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** + 44:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** /** \file */ + 45:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** /** \defgroup util_delay_basic : Basic busy-wait delay loops + 46:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** \code + 47:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** #include + 48:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** \endcode + 49:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** + 50:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** The functions in this header file implement simple delay loops + 51:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** that perform a busy-waiting. They are typically used to + 52:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** facilitate short delays in the program execution. They are + 53:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** implemented as count-down loops with a well-known CPU cycle + 54:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** count per loop iteration. As such, no other processing can + 55:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** occur simultaneously. It should be kept in mind that the + 56:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** functions described here do not disable interrupts. + 57:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** + 58:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** In general, for long delays, the use of hardware timers is + 59:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** much preferrable, as they free the CPU, and allow for + 60:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** concurrent processing of other events while the timer is + 61:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** running. However, in particular for very short delays, the + 62:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** overhead of setting up a hardware timer is too much compared + 63:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** to the overall delay time. + 64:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** + 65:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** Two inline functions are provided for the actual delay algorithms. + 66:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** + 67:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** */ + 68:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** + 69:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** /** \ingroup util_delay_basic + 70:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** + 71:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** Delay loop using an 8-bit counter \c __count, so up to 256 + 72:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** iterations are possible. (The value 256 would have to be passed + 73:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** as 0.) The loop executes three CPU cycles per iteration, not + 74:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** including the overhead the compiler needs to setup the counter + 75:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** register. + 76:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** + 77:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** Thus, at a CPU speed of 1 MHz, delays of up to 768 microseconds + 78:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** can be achieved. + 79:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** */ + 80:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** void + 81:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** _delay_loop_1(uint8_t __count) + 82:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** { + 83:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** __asm__ volatile ( + 84:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** "1: dec %0" "\n\t" + 85:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** "brne 1b" + 86:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** : "=r" (__count) + 87:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** : "0" (__count) + 88:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** ); + 89:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** } + 90:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** + 91:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** /** \ingroup util_delay_basic + 92:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** + 93:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** Delay loop using a 16-bit counter \c __count, so up to 65536 + 94:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** iterations are possible. (The value 65536 would have to be + 95:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** passed as 0.) The loop executes four CPU cycles per iteration, + 96:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** not including the overhead the compiler requires to setup the + 97:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** counter register pair. + 98:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** + 99:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** Thus, at a CPU speed of 1 MHz, delays of up to about 262.1 + 100:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** milliseconds can be achieved. + 101:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** */ + 102:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** void + 103:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** _delay_loop_2(uint16_t __count) + 104:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** { + 105:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic.h **** __asm__ volatile ( + 129 .loc 2 105 0 + 130 004a 20E9 ldi r18,lo8(400) + 131 004c 31E0 ldi r19,hi8(400) + 132 .LVL3: + 133 .L7: + 134 004e F901 movw r30,r18 + 135 /* #APP */ + 136 ; 105 "/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic + 137 0050 3197 1: sbiw r30,1 + 138 0052 01F4 brne 1b + 139 ; 0 "" 2 + 140 .LVL4: + 141 /* #NOAPP */ + 142 0054 0197 sbiw r24,1 + 143 .LBE27: + 144 .LBE26: + 145 .file 3 "/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h" + 1:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** /* Copyright (c) 2002, Marek Michalkiewicz + 2:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** Copyright (c) 2004,2005,2007 Joerg Wunsch + 3:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** Copyright (c) 2007 Florin-Viorel Petrov + 4:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** All rights reserved. + 5:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 6:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** Redistribution and use in source and binary forms, with or without + 7:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** modification, are permitted provided that the following conditions are met: + 8:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 9:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** * Redistributions of source code must retain the above copyright + 10:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** notice, this list of conditions and the following disclaimer. + 11:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 12:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** * Redistributions in binary form must reproduce the above copyright + 13:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** notice, this list of conditions and the following disclaimer in + 14:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** the documentation and/or other materials provided with the + 15:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** distribution. + 16:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 17:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** * Neither the name of the copyright holders nor the names of + 18:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** contributors may be used to endorse or promote products derived + 19:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** from this software without specific prior written permission. + 20:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 21:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + 22:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + 23:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + 24:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + 25:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + 26:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + 27:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + 28:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + 29:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + 30:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + 31:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** POSSIBILITY OF SUCH DAMAGE. */ + 32:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 33:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** /* $Id: delay.h.in 2189 2010-10-13 09:39:34Z aboyapati $ */ + 34:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 35:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** #ifndef _UTIL_DELAY_H_ + 36:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** #define _UTIL_DELAY_H_ 1 + 37:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 38:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** #ifndef __HAS_DELAY_CYCLES + 39:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** #define __HAS_DELAY_CYCLES 0 + 40:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** #endif + 41:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 42:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** #include + 43:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** #include + 44:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 45:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** /** \file */ + 46:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** /** \defgroup util_delay : Convenience functions for busy-wait delay loops + 47:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** \code + 48:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** #define F_CPU 1000000UL // 1 MHz + 49:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** //#define F_CPU 14.7456E6 + 50:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** #include + 51:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** \endcode + 52:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 53:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** \note As an alternative method, it is possible to pass the + 54:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** F_CPU macro down to the compiler from the Makefile. + 55:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** Obviously, in that case, no \c \#define statement should be + 56:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** used. + 57:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 58:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** The functions in this header file are wrappers around the basic + 59:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** busy-wait functions from . They are meant as + 60:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** convenience functions where actual time values can be specified + 61:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** rather than a number of cycles to wait for. The idea behind is + 62:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** that compile-time constant expressions will be eliminated by + 63:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** compiler optimization so floating-point expressions can be used + 64:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** to calculate the number of delay cycles needed based on the CPU + 65:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** frequency passed by the macro F_CPU. + 66:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 67:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** \note In order for these functions to work as intended, compiler + 68:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** optimizations must be enabled, and the delay time + 69:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** must be an expression that is a known constant at + 70:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** compile-time. If these requirements are not met, the resulting + 71:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** delay will be much longer (and basically unpredictable), and + 72:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** applications that otherwise do not use floating-point calculations + 73:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** will experience severe code bloat by the floating-point library + 74:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** routines linked into the application. + 75:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 76:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** The functions available allow the specification of microsecond, and + 77:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** millisecond delays directly, using the application-supplied macro + 78:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** F_CPU as the CPU clock frequency (in Hertz). + 79:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 80:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** */ + 81:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 82:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** #if !defined(__DOXYGEN__) + 83:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** static inline void _delay_us(double __us) __attribute__((always_inline)); + 84:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** static inline void _delay_ms(double __ms) __attribute__((always_inline)); + 85:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** #endif + 86:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 87:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** #ifndef F_CPU + 88:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** /* prevent compiler error by supplying a default */ + 89:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** # warning "F_CPU not defined for " + 90:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** # define F_CPU 1000000UL + 91:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** #endif + 92:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 93:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** #ifndef __OPTIMIZE__ + 94:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** # warning "Compiler optimizations disabled; functions from won't work as designed" + 95:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** #endif + 96:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 97:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** /** + 98:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** \ingroup util_delay + 99:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 100:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** Perform a delay of \c __ms milliseconds, using _delay_loop_2(). + 101:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 102:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** The macro F_CPU is supposed to be defined to a + 103:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** constant defining the CPU clock frequency (in Hertz). + 104:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 105:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** The maximal possible delay is 262.14 ms / F_CPU in MHz. + 106:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 107:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** When the user request delay which exceed the maximum possible one, + 108:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** _delay_ms() provides a decreased resolution functionality. In this + 109:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** mode _delay_ms() will work with a resolution of 1/10 ms, providing + 110:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** delays up to 6.5535 seconds (independent from CPU frequency). The + 111:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** user will not be informed about decreased resolution. + 112:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 113:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** If the avr-gcc toolchain has __builtin_avr_delay_cycles(unsigned long) + 114:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** support, maximal possible delay is 4294967.295 ms/ F_CPU in MHz. For + 115:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** values greater than the maximal possible delay, overflows results in + 116:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** no delay i.e., 0ms. + 117:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 118:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** Conversion of __us into clock cycles may not always result in integer. + 119:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** By default, the clock cycles rounded up to next integer. This ensures that + 120:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** the user gets atleast __us microseconds of delay. + 121:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 122:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** Alternatively, user can define __DELAY_ROUND_DOWN__ and __DELAY_ROUND_CLOSEST__ + 123:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** to round down and round to closest integer. + 124:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 125:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** Note: The new implementation of _delay_ms(double __ms) with + 126:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** __builtin_avr_delay_cycles(unsigned long) support is not backward compatible. + 127:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** User can define __DELAY_BACKWARD_COMPATIBLE__ to get a backward compatible delay + 128:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** although this will be deprecated in future. + 129:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 130:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** */ + 131:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** void + 132:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** _delay_ms(double __ms) + 133:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** { + 134:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** uint16_t __ticks; + 135:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** double __tmp ; + 136:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** #if __HAS_DELAY_CYCLES && defined(__OPTIMIZE__) && !defined(__DELAY_BACKWARD_COMPATIBLE__) + 137:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** uint32_t __ticks_dc; + 138:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** extern void __builtin_avr_delay_cycles(unsigned long); + 139:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** __tmp = ((F_CPU) / 1e3) * __ms; + 140:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 141:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** #if defined(__DELAY_ROUND_DOWN__) + 142:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** __ticks_dc = (uint32_t)fabs(__tmp); + 143:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 144:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** #elif defined(__DELAY_ROUND_CLOSEST__) + 145:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** __ticks_dc = (uint32_t)(fabs(__tmp)+0.5); + 146:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 147:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** #else + 148:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** //round up by default + 149:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** __ticks_dc = (uint32_t)(ceil(fabs(__tmp))); + 150:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** #endif + 151:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 152:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** __builtin_avr_delay_cycles(__ticks_dc); + 153:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** + 154:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** #elif !__HAS_DELAY_CYCLES || (__HAS_DELAY_CYCLES && !defined(__OPTIMIZE__)) || defined (__DELAY_BAC + 155:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** __tmp = ((F_CPU) / 4e3) * __ms; + 156:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** if (__tmp < 1.0) + 157:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** __ticks = 1; + 158:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** else if (__tmp > 65535) + 159:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** { + 160:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** // __ticks = requested delay in 1/10 ms + 161:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** __ticks = (uint16_t) (__ms * 10.0); + 162:/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay.h **** while(__ticks) + 146 .loc 3 162 0 + 147 0056 01F4 brne .L7 + 148 0058 00E0 ldi r16,lo8(0) + 149 005a 10E0 ldi r17,hi8(0) + 150 .LBE25: + 151 .LBE24: + 152 .LBB28: + 82:main.c **** _delay_ms(5000); + 83:main.c **** + 84:main.c **** while (1) { + 85:main.c **** for(uint16_t i = 0; i < 0xffff; i++) { + 86:main.c **** + 87:main.c **** /* Print the number to serial for debugging. */ + 88:main.c **** itoa(i, binary, 2); + 153 .loc 1 88 0 + 154 005c 7E01 movw r14,r28 + 155 005e 0894 sec + 156 0060 E11C adc r14,__zero_reg__ + 157 0062 F11C adc r15,__zero_reg__ + 89:main.c **** printf("%s %d \n", binary, i); + 158 .loc 1 89 0 + 159 0064 80E0 ldi r24,lo8(.LC0) + 160 0066 C82E mov r12,r24 + 161 0068 80E0 ldi r24,hi8(.LC0) + 162 006a D82E mov r13,r24 + 163 .LBB29: + 164 .LBB30: + 165 .LBB31: + 166 .LBB32: + 167 .loc 2 105 0 + 168 006c 90E9 ldi r25,lo8(400) + 169 006e A92E mov r10,r25 + 170 0070 91E0 ldi r25,hi8(400) + 171 0072 B92E mov r11,r25 + 172 .L15: + 173 .LBE32: + 174 .LBE31: + 175 .LBE30: + 176 .LBE29: + 88:main.c **** itoa(i, binary, 2); + 177 .loc 1 88 0 discriminator 2 + 178 0074 C801 movw r24,r16 + 179 0076 B701 movw r22,r14 + 180 0078 42E0 ldi r20,lo8(2) + 181 007a 50E0 ldi r21,hi8(2) + 182 007c 0E94 0000 call itoa + 183 .loc 1 89 0 discriminator 2 + 184 0080 00D0 rcall . + 185 0082 00D0 rcall . + 186 0084 00D0 rcall . + 187 0086 EDB7 in r30,__SP_L__ + 188 0088 FEB7 in r31,__SP_H__ + 189 008a 3196 adiw r30,1 + 190 008c ADB7 in r26,__SP_L__ + 191 008e BEB7 in r27,__SP_H__ + 192 0090 1296 adiw r26,1+1 + 193 0092 DC92 st X,r13 + 194 0094 CE92 st -X,r12 + 195 0096 1197 sbiw r26,1 + 196 0098 F382 std Z+3,r15 + 197 009a E282 std Z+2,r14 + 198 009c 1583 std Z+5,r17 + 199 009e 0483 std Z+4,r16 + 200 .LCFI3: + 201 00a0 0E94 0000 call printf + 90:main.c **** + 91:main.c **** /* Shift high byte first to shift register. */ + 92:main.c **** shift_out(i >> 8); + 202 .loc 1 92 0 discriminator 2 + 203 00a4 8DB7 in r24,__SP_L__ + 204 00a6 9EB7 in r25,__SP_H__ + 205 00a8 0696 adiw r24,6 + 206 00aa 0FB6 in __tmp_reg__,__SREG__ + 207 00ac F894 cli + 208 00ae 9EBF out __SP_H__,r25 + 209 00b0 0FBE out __SREG__,__tmp_reg__ + 210 00b2 8DBF out __SP_L__,r24 + 211 00b4 812F mov r24,r17 + 212 .LCFI4: + 213 00b6 0E94 0000 call shift_out + 93:main.c **** shift_out(i & 0xff); + 214 .loc 1 93 0 discriminator 2 + 215 00ba 802F mov r24,r16 + 216 00bc 0E94 0000 call shift_out + 94:main.c **** + 95:main.c **** /* Pulse latch to transfer data from shift registers */ + 96:main.c **** /* to storage registers (should this be inside shift_out()?). */ + 97:main.c **** digital_write(LATCH, LOW); + 217 .loc 1 97 0 discriminator 2 + 218 00c0 2A98 cbi 37-0x20,2 + 98:main.c **** digital_write(LATCH, HIGH); + 219 .loc 1 98 0 discriminator 2 + 220 00c2 2A9A sbi 37-0x20,2 + 221 .LVL5: + 222 00c4 24EF ldi r18,lo8(500) + 223 00c6 31E0 ldi r19,hi8(500) + 224 .LVL6: + 225 .L9: + 226 .LBB36: + 227 .LBB35: + 228 .LBB34: + 229 .LBB33: + 230 .loc 2 105 0 + 231 00c8 C501 movw r24,r10 + 232 /* #APP */ + 233 ; 105 "/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/util/delay_basic + 234 00ca 0197 1: sbiw r24,1 + 235 00cc 01F4 brne 1b + 236 ; 0 "" 2 + 237 .LVL7: + 238 /* #NOAPP */ + 239 00ce 2150 subi r18,lo8(-(-1)) + 240 00d0 3040 sbci r19,hi8(-(-1)) + 241 .LBE33: + 242 .LBE34: + 243 .loc 3 162 0 + 244 00d2 01F4 brne .L9 + 245 .LBE35: + 246 .LBE36: + 85:main.c **** for(uint16_t i = 0; i < 0xffff; i++) { + 247 .loc 1 85 0 discriminator 2 + 248 00d4 0F5F subi r16,lo8(-(1)) + 249 00d6 1F4F sbci r17,hi8(-(1)) + 250 .LVL8: + 251 00d8 9FEF ldi r25,hi8(-1) + 252 00da 0F3F cpi r16,lo8(-1) + 253 00dc 1907 cpc r17,r25 + 254 00de 01F4 brne .L15 + 85:main.c **** for(uint16_t i = 0; i < 0xffff; i++) { + 255 .loc 1 85 0 is_stmt 0 + 256 00e0 00E0 ldi r16,lo8(0) + 257 00e2 10E0 ldi r17,hi8(0) + 258 .LVL9: + 259 00e4 00C0 rjmp .L15 + 260 .LBE28: + 261 .LFE7: + 263 .global uart_input + 264 .data + 267 uart_input: + 268 0008 0000 00 .skip 3,0 + 269 000b 01 .byte 1 + 270 000c 0000 0000 .skip 4,0 + 271 0010 0000 .word 0 + 272 0012 0000 .word gs(uart_getchar) + 273 0014 0000 .word 0 + 274 .global uart_output + 277 uart_output: + 278 0016 0000 00 .skip 3,0 + 279 0019 02 .byte 2 + 280 001a 0000 0000 .skip 4,0 + 281 001e 0000 .word gs(uart_putchar) + 282 0020 0000 .word 0 + 283 0022 0000 .word 0 + 343 .Letext0: + 344 .file 4 "/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/stdint.h" + 345 .file 5 "/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/stdio.h" + 346 .file 6 "uart.h" +DEFINED SYMBOLS + *ABS*:0000000000000000 main.c +/var/folders/6p/hvps1d6n58jfd6qghfhb96600000gn/T//cclunMq8.s:2 *ABS*:000000000000003f __SREG__ +/var/folders/6p/hvps1d6n58jfd6qghfhb96600000gn/T//cclunMq8.s:3 *ABS*:000000000000003e __SP_H__ +/var/folders/6p/hvps1d6n58jfd6qghfhb96600000gn/T//cclunMq8.s:4 *ABS*:000000000000003d __SP_L__ +/var/folders/6p/hvps1d6n58jfd6qghfhb96600000gn/T//cclunMq8.s:5 *ABS*:0000000000000000 __tmp_reg__ +/var/folders/6p/hvps1d6n58jfd6qghfhb96600000gn/T//cclunMq8.s:6 *ABS*:0000000000000001 __zero_reg__ +/var/folders/6p/hvps1d6n58jfd6qghfhb96600000gn/T//cclunMq8.s:13 .text:0000000000000000 shift_out +/var/folders/6p/hvps1d6n58jfd6qghfhb96600000gn/T//cclunMq8.s:69 .text.startup:0000000000000000 main +/var/folders/6p/hvps1d6n58jfd6qghfhb96600000gn/T//cclunMq8.s:277 .data:0000000000000016 uart_output +/var/folders/6p/hvps1d6n58jfd6qghfhb96600000gn/T//cclunMq8.s:267 .data:0000000000000008 uart_input + +UNDEFINED SYMBOLS +__do_copy_data +__do_clear_bss +uart_init +__iob +itoa +printf +uart_getchar +uart_putchar diff --git a/tpic6b595_shiftout/main.map b/tpic6b595_shiftout/main.map new file mode 100644 index 0000000..002df2c --- /dev/null +++ b/tpic6b595_shiftout/main.map @@ -0,0 +1,659 @@ +Archive member included because of file (symbol) + +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/avr5/libgcc.a(_divmodhi4.o) + uart_async.o (__divmodhi4) +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/avr5/libgcc.a(_exit.o) + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/lib/avr5/crtm328p.o (exit) +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/avr5/libgcc.a(_copy_data.o) + main.o (__do_copy_data) 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/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/lib/avr5/libc.a(vfprintf_std.o) (strnlen_P) +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/lib/avr5/libc.a(strnlen.o) + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/lib/avr5/libc.a(vfprintf_std.o) (strnlen) +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/lib/avr5/libc.a(strrev.o) + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/lib/avr5/libc.a(itoa.o) (strrev) +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/lib/avr5/libc.a(fputc.o) + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/lib/avr5/libc.a(vfprintf_std.o) (fputc) +/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/lib/avr5/libc.a(ultoa_invert.o) + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/lib/avr5/libc.a(vfprintf_std.o) (__ultoa_invert) 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/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/avr5/libgcc.a(_divmodhi4.o) +_exit /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/avr5/libgcc.a(_exit.o) +exit /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/avr5/libgcc.a(_exit.o) + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/lib/avr5/crtm328p.o +fputc /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/lib/avr5/libc.a(fputc.o) + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/lib/avr5/libc.a(vfprintf_std.o) +itoa /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/lib/avr5/libc.a(itoa.o) + main.o +main main.o + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/lib/avr5/crtm328p.o +printf /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/lib/avr5/libc.a(printf.o) + main.o +shift_out main.o +strnlen /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/lib/avr5/libc.a(strnlen.o) + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/lib/avr5/libc.a(vfprintf_std.o) +strnlen_P /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/lib/avr5/libc.a(strnlen_P.o) + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/lib/avr5/libc.a(vfprintf_std.o) +strrev /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/lib/avr5/libc.a(strrev.o) + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/lib/avr5/libc.a(itoa.o) +uart_getchar uart_async.o + main.o +uart_init uart_async.o + main.o +uart_input main.o +uart_output main.o +uart_putchar uart_async.o + main.o +vfprintf /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/lib/avr5/libc.a(vfprintf_std.o) + /usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/lib/avr5/libc.a(printf.o) diff --git a/tpic6b595_shiftout/main.o b/tpic6b595_shiftout/main.o new file mode 100644 index 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z>}HJ0Kt1Ym9yuQ3JUH`ZVlo8rZ@^7m`m6Iw`v + 4:uart_async.c **** #include + 5:uart_async.c **** #include + 6:uart_async.c **** + 7:uart_async.c **** #ifndef BAUD + 8:uart_async.c **** #define BAUD 9600 + 9:uart_async.c **** #endif + 10:uart_async.c **** #include + 11:uart_async.c **** + 12:uart_async.c **** #ifndef UART_RX_BUFFER_SIZE + 13:uart_async.c **** #define UART_RX_BUFFER_SIZE 32 + 14:uart_async.c **** #endif + 15:uart_async.c **** + 16:uart_async.c **** #ifndef UART_TX_BUFFER_SIZE + 17:uart_async.c **** #define UART_TX_BUFFER_SIZE 512 + 18:uart_async.c **** #endif + 19:uart_async.c **** + 20:uart_async.c **** struct tx_ring { + 21:uart_async.c **** int buffer[UART_TX_BUFFER_SIZE]; + 22:uart_async.c **** int start; + 23:uart_async.c **** int end; + 24:uart_async.c **** }; + 25:uart_async.c **** + 26:uart_async.c **** struct rx_ring { + 27:uart_async.c **** int buffer[UART_RX_BUFFER_SIZE]; + 28:uart_async.c **** int start; + 29:uart_async.c **** int end; + 30:uart_async.c **** }; + 31:uart_async.c **** + 32:uart_async.c **** static struct tx_ring tx_buffer; + 33:uart_async.c **** static struct rx_ring rx_buffer; + 34:uart_async.c **** + 35:uart_async.c **** /* http://www.cs.mun.ca/~rod/Winter2007/4723/notes/serial/serial.html */ + 36:uart_async.c **** + 37:uart_async.c **** void uart_init(void) { + 16 .loc 1 37 0 + 17 /* prologue: function */ + 18 /* frame size = 0 */ + 19 /* stack size = 0 */ + 20 .L__stack_usage = 0 + 38:uart_async.c **** + 39:uart_async.c **** tx_buffer.start = 0; + 21 .loc 1 39 0 + 22 0000 1092 0000 sts tx_buffer+1024+1,__zero_reg__ + 23 0004 1092 0000 sts tx_buffer+1024,__zero_reg__ + 40:uart_async.c **** tx_buffer.end = 0; + 24 .loc 1 40 0 + 25 0008 1092 0000 sts tx_buffer+1026+1,__zero_reg__ + 26 000c 1092 0000 sts tx_buffer+1026,__zero_reg__ + 41:uart_async.c **** + 42:uart_async.c **** rx_buffer.start = 0; + 27 .loc 1 42 0 + 28 0010 1092 0000 sts rx_buffer+64+1,__zero_reg__ + 29 0014 1092 0000 sts rx_buffer+64,__zero_reg__ + 43:uart_async.c **** rx_buffer.end = 0; + 30 .loc 1 43 0 + 31 0018 1092 0000 sts rx_buffer+66+1,__zero_reg__ + 32 001c 1092 0000 sts rx_buffer+66,__zero_reg__ + 44:uart_async.c **** + 45:uart_async.c **** UBRR0H = UBRRH_VALUE; + 33 .loc 1 45 0 + 34 0020 1092 C500 sts 197,__zero_reg__ + 46:uart_async.c **** UBRR0L = UBRRL_VALUE; + 35 .loc 1 46 0 + 36 0024 87E6 ldi r24,lo8(103) + 37 0026 8093 C400 sts 196,r24 + 47:uart_async.c **** + 48:uart_async.c **** UCSR0C = _BV(UCSZ01) | _BV(UCSZ00); /* 8-bit data */ + 38 .loc 1 48 0 + 39 002a 86E0 ldi r24,lo8(6) + 40 002c 8093 C200 sts 194,r24 + 49:uart_async.c **** UCSR0B = _BV(RXEN0) | _BV(TXEN0); /* Enable RX and TX */ + 41 .loc 1 49 0 + 42 0030 88E1 ldi r24,lo8(24) + 43 0032 8093 C100 sts 193,r24 + 50:uart_async.c **** + 51:uart_async.c **** sei(); + 44 .loc 1 51 0 + 45 /* #APP */ + 46 ; 51 "uart_async.c" 1 + 47 0036 7894 sei + 48 ; 0 "" 2 + 49 /* epilogue start */ + 52:uart_async.c **** } + 50 .loc 1 52 0 + 51 /* #NOAPP */ + 52 0038 0895 ret + 53 .LFE1: + 55 .global uart_putchar + 57 uart_putchar: + 58 .LFB2: + 53:uart_async.c **** + 54:uart_async.c **** int uart_putchar(char c, FILE *stream) { + 59 .loc 1 54 0 + 60 .LVL0: + 61 003a 1F93 push r17 + 62 .LCFI0: + 63 /* prologue: function */ + 64 /* frame size = 0 */ + 65 /* stack size = 1 */ + 66 .L__stack_usage = 1 + 67 003c 182F mov r17,r24 + 55:uart_async.c **** if (c == '\n') { + 68 .loc 1 55 0 + 69 003e 8A30 cpi r24,lo8(10) + 70 0040 01F4 brne .L3 + 71 .LVL1: + 56:uart_async.c **** uart_putchar('\r', stream); + 72 .loc 1 56 0 + 73 0042 8DE0 ldi r24,lo8(13) + 74 0044 0E94 0000 call uart_putchar + 75 .LVL2: + 76 .L3: + 57:uart_async.c **** } + 58:uart_async.c **** + 59:uart_async.c **** int write_pointer = (tx_buffer.end + 1) % UART_TX_BUFFER_SIZE; + 77 .loc 1 59 0 + 78 0048 2091 0000 lds r18,tx_buffer+1026 + 79 004c 3091 0000 lds r19,tx_buffer+1026+1 + 80 0050 C901 movw r24,r18 + 81 0052 0196 adiw r24,1 + 82 0054 60E0 ldi r22,lo8(512) + 83 0056 72E0 ldi r23,hi8(512) + 84 0058 0E94 0000 call __divmodhi4 + 85 .LVL3: + 60:uart_async.c **** + 61:uart_async.c **** if (write_pointer != tx_buffer.start){ + 86 .loc 1 61 0 + 87 005c 4091 0000 lds r20,tx_buffer+1024 + 88 0060 5091 0000 lds r21,tx_buffer+1024+1 + 89 0064 8417 cp r24,r20 + 90 0066 9507 cpc r25,r21 + 91 0068 01F0 breq .L4 + 62:uart_async.c **** tx_buffer.buffer[tx_buffer.end] = c; + 92 .loc 1 62 0 + 93 006a F901 movw r30,r18 + 94 006c EE0F lsl r30 + 95 006e FF1F rol r31 + 96 0070 E050 subi r30,lo8(-(tx_buffer)) + 97 0072 F040 sbci r31,hi8(-(tx_buffer)) + 98 0074 1083 st Z,r17 + 99 0076 1182 std Z+1,__zero_reg__ + 63:uart_async.c **** tx_buffer.end = write_pointer; + 100 .loc 1 63 0 + 101 0078 9093 0000 sts tx_buffer+1026+1,r25 + 102 007c 8093 0000 sts tx_buffer+1026,r24 + 64:uart_async.c **** + 65:uart_async.c **** /* Data available. Enable the transmit interrupt for serial port 0. */ + 66:uart_async.c **** UCSR0B |= _BV(UDRIE0); + 103 .loc 1 66 0 + 104 0080 8091 C100 lds r24,193 + 105 .LVL4: + 106 0084 8062 ori r24,lo8(32) + 107 0086 8093 C100 sts 193,r24 + 108 .LVL5: + 109 .L4: + 67:uart_async.c **** } + 68:uart_async.c **** + 69:uart_async.c **** return 0; + 70:uart_async.c **** } + 110 .loc 1 70 0 + 111 008a 80E0 ldi r24,lo8(0) + 112 008c 90E0 ldi r25,hi8(0) + 113 /* epilogue start */ + 114 008e 1F91 pop r17 + 115 .LVL6: + 116 0090 0895 ret + 117 .LFE2: + 119 .global uart_getchar + 121 uart_getchar: + 122 .LFB3: + 71:uart_async.c **** + 72:uart_async.c **** int uart_getchar(FILE *stream) { + 123 .loc 1 72 0 + 124 .LVL7: + 125 /* prologue: function */ + 126 /* frame size = 0 */ + 127 /* stack size = 0 */ + 128 .L__stack_usage = 0 + 73:uart_async.c **** int read_pointer = (rx_buffer.start + 1) % UART_RX_BUFFER_SIZE; + 129 .loc 1 73 0 + 130 0092 8091 0000 lds r24,rx_buffer+64 + 131 0096 9091 0000 lds r25,rx_buffer+64+1 + 132 .LVL8: + 133 009a 0196 adiw r24,1 + 134 009c 60E2 ldi r22,lo8(32) + 135 009e 70E0 ldi r23,hi8(32) + 136 00a0 0E94 0000 call __divmodhi4 + 137 .LVL9: + 74:uart_async.c **** + 75:uart_async.c **** rx_buffer.start = read_pointer; + 138 .loc 1 75 0 + 139 00a4 9093 0000 sts rx_buffer+64+1,r25 + 140 00a8 8093 0000 sts rx_buffer+64,r24 + 76:uart_async.c **** return rx_buffer.buffer[read_pointer]; + 141 .loc 1 76 0 + 142 00ac FC01 movw r30,r24 + 143 00ae EE0F lsl r30 + 144 00b0 FF1F rol r31 + 145 00b2 E050 subi r30,lo8(-(rx_buffer)) + 146 00b4 F040 sbci r31,hi8(-(rx_buffer)) + 77:uart_async.c **** } + 147 .loc 1 77 0 + 148 00b6 8081 ld r24,Z + 149 .LVL10: + 150 00b8 9181 ldd r25,Z+1 + 151 /* epilogue start */ + 152 00ba 0895 ret + 153 .LFE3: + 155 .global __vector_18 + 157 __vector_18: + 158 .LFB4: + 78:uart_async.c **** + 79:uart_async.c **** ISR(USART_RX_vect) { + 159 .loc 1 79 0 + 160 00bc 1F92 push r1 + 161 .LCFI1: + 162 00be 0F92 push r0 + 163 .LCFI2: + 164 00c0 0FB6 in r0,__SREG__ + 165 00c2 0F92 push r0 + 166 00c4 1124 clr __zero_reg__ + 167 00c6 2F93 push r18 + 168 .LCFI3: + 169 00c8 3F93 push r19 + 170 .LCFI4: + 171 00ca 4F93 push r20 + 172 .LCFI5: + 173 00cc 5F93 push r21 + 174 .LCFI6: + 175 00ce 6F93 push r22 + 176 .LCFI7: + 177 00d0 7F93 push r23 + 178 .LCFI8: + 179 00d2 8F93 push r24 + 180 .LCFI9: + 181 00d4 9F93 push r25 + 182 .LCFI10: + 183 00d6 AF93 push r26 + 184 .LCFI11: + 185 00d8 BF93 push r27 + 186 .LCFI12: + 187 00da EF93 push r30 + 188 .LCFI13: + 189 00dc FF93 push r31 + 190 .LCFI14: + 191 /* prologue: Signal */ + 192 /* frame size = 0 */ + 193 /* stack size = 15 */ + 194 .L__stack_usage = 15 + 80:uart_async.c **** int write_pointer = (rx_buffer.end + 1) % UART_RX_BUFFER_SIZE; + 195 .loc 1 80 0 + 196 00de 2091 0000 lds r18,rx_buffer+66 + 197 00e2 3091 0000 lds r19,rx_buffer+66+1 + 198 00e6 C901 movw r24,r18 + 199 00e8 0196 adiw r24,1 + 200 00ea 60E2 ldi r22,lo8(32) + 201 00ec 70E0 ldi r23,hi8(32) + 202 00ee 0E94 0000 call __divmodhi4 + 203 .LVL11: + 81:uart_async.c **** + 82:uart_async.c **** /* Add next byte to ringbuffer if it has space available. */ + 83:uart_async.c **** if (write_pointer != rx_buffer.start){ + 204 .loc 1 83 0 + 205 00f2 4091 0000 lds r20,rx_buffer+64 + 206 00f6 5091 0000 lds r21,rx_buffer+64+1 + 207 00fa 8417 cp r24,r20 + 208 00fc 9507 cpc r25,r21 + 209 00fe 01F0 breq .L6 + 84:uart_async.c **** rx_buffer.buffer[rx_buffer.end] = UDR0; + 210 .loc 1 84 0 + 211 0100 4091 C600 lds r20,198 + 212 0104 F901 movw r30,r18 + 213 0106 EE0F lsl r30 + 214 0108 FF1F rol r31 + 215 010a E050 subi r30,lo8(-(rx_buffer)) + 216 010c F040 sbci r31,hi8(-(rx_buffer)) + 217 010e 4083 st Z,r20 + 218 0110 1182 std Z+1,__zero_reg__ + 85:uart_async.c **** rx_buffer.end = write_pointer; + 219 .loc 1 85 0 + 220 0112 9093 0000 sts rx_buffer+66+1,r25 + 221 0116 8093 0000 sts rx_buffer+66,r24 + 222 .L6: + 223 /* epilogue start */ + 86:uart_async.c **** } + 87:uart_async.c **** } + 224 .loc 1 87 0 + 225 011a FF91 pop r31 + 226 011c EF91 pop r30 + 227 011e BF91 pop r27 + 228 0120 AF91 pop r26 + 229 0122 9F91 pop r25 + 230 0124 8F91 pop r24 + 231 .LVL12: + 232 0126 7F91 pop r23 + 233 0128 6F91 pop r22 + 234 012a 5F91 pop r21 + 235 012c 4F91 pop r20 + 236 012e 3F91 pop r19 + 237 0130 2F91 pop r18 + 238 0132 0F90 pop r0 + 239 0134 0FBE out __SREG__,r0 + 240 0136 0F90 pop r0 + 241 0138 1F90 pop r1 + 242 013a 1895 reti + 243 .LFE4: + 245 .global __vector_19 + 247 __vector_19: + 248 .LFB5: + 88:uart_async.c **** + 89:uart_async.c **** ISR(USART_UDRE_vect){ + 249 .loc 1 89 0 + 250 013c 1F92 push r1 + 251 .LCFI15: + 252 013e 0F92 push r0 + 253 .LCFI16: + 254 0140 0FB6 in r0,__SREG__ + 255 0142 0F92 push r0 + 256 0144 1124 clr __zero_reg__ + 257 0146 2F93 push r18 + 258 .LCFI17: + 259 0148 3F93 push r19 + 260 .LCFI18: + 261 014a 5F93 push r21 + 262 .LCFI19: + 263 014c 6F93 push r22 + 264 .LCFI20: + 265 014e 7F93 push r23 + 266 .LCFI21: + 267 0150 8F93 push r24 + 268 .LCFI22: + 269 0152 9F93 push r25 + 270 .LCFI23: + 271 0154 AF93 push r26 + 272 .LCFI24: + 273 0156 BF93 push r27 + 274 .LCFI25: + 275 0158 EF93 push r30 + 276 .LCFI26: + 277 015a FF93 push r31 + 278 .LCFI27: + 279 /* prologue: Signal */ + 280 /* frame size = 0 */ + 281 /* stack size = 14 */ + 282 .L__stack_usage = 14 + 90:uart_async.c **** int read_pointer = (tx_buffer.start + 1) % UART_TX_BUFFER_SIZE; + 283 .loc 1 90 0 + 284 015c 8091 0000 lds r24,tx_buffer+1024 + 285 0160 9091 0000 lds r25,tx_buffer+1024+1 + 286 0164 0196 adiw r24,1 + 287 0166 60E0 ldi r22,lo8(512) + 288 0168 72E0 ldi r23,hi8(512) + 289 016a 0E94 0000 call __divmodhi4 + 290 .LVL13: + 91:uart_async.c **** + 92:uart_async.c **** /* Transmit next byte if data available in ringbuffer. */ + 93:uart_async.c **** if (read_pointer != tx_buffer.end) { + 291 .loc 1 93 0 + 292 016e 2091 0000 lds r18,tx_buffer+1026 + 293 0172 3091 0000 lds r19,tx_buffer+1026+1 + 294 0176 8217 cp r24,r18 + 295 0178 9307 cpc r25,r19 + 296 017a 01F0 breq .L9 + 94:uart_async.c **** UDR0 = tx_buffer.buffer[read_pointer]; + 297 .loc 1 94 0 + 298 017c FC01 movw r30,r24 + 299 017e EE0F lsl r30 + 300 0180 FF1F rol r31 + 301 0182 E050 subi r30,lo8(-(tx_buffer)) + 302 0184 F040 sbci r31,hi8(-(tx_buffer)) + 303 0186 2081 ld r18,Z + 304 0188 2093 C600 sts 198,r18 + 95:uart_async.c **** tx_buffer.start = read_pointer; + 305 .loc 1 95 0 + 306 018c 9093 0000 sts tx_buffer+1024+1,r25 + 307 0190 8093 0000 sts tx_buffer+1024,r24 + 308 0194 00C0 rjmp .L8 + 309 .L9: + 96:uart_async.c **** } else { + 97:uart_async.c **** /* Nothing to send. Disable the transmit interrupt for serial port 0. */ + 98:uart_async.c **** UCSR0B &= ~_BV(UDRIE0); + 310 .loc 1 98 0 + 311 0196 8091 C100 lds r24,193 + 312 .LVL14: + 313 019a 8F7D andi r24,lo8(-33) + 314 019c 8093 C100 sts 193,r24 + 315 .L8: + 316 /* epilogue start */ + 99:uart_async.c **** } + 100:uart_async.c **** } + 317 .loc 1 100 0 + 318 01a0 FF91 pop r31 + 319 01a2 EF91 pop r30 + 320 01a4 BF91 pop r27 + 321 01a6 AF91 pop r26 + 322 01a8 9F91 pop r25 + 323 01aa 8F91 pop r24 + 324 01ac 7F91 pop r23 + 325 01ae 6F91 pop r22 + 326 01b0 5F91 pop r21 + 327 01b2 3F91 pop r19 + 328 01b4 2F91 pop r18 + 329 01b6 0F90 pop r0 + 330 01b8 0FBE out __SREG__,r0 + 331 01ba 0F90 pop r0 + 332 01bc 1F90 pop r1 + 333 01be 1895 reti + 334 .LFE5: + 336 .lcomm tx_buffer,1028 + 337 .lcomm rx_buffer,68 + 564 .Letext0: + 565 .file 2 "/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/stdio.h" + 566 .file 3 "/usr/local/Cellar/avr-gcc/4.6.1/lib/gcc/avr/4.6.1/../../../../avr/include/stdint.h" +DEFINED SYMBOLS + *ABS*:0000000000000000 uart_async.c +/var/folders/6p/hvps1d6n58jfd6qghfhb96600000gn/T//cchq05jZ.s:2 *ABS*:000000000000003f __SREG__ +/var/folders/6p/hvps1d6n58jfd6qghfhb96600000gn/T//cchq05jZ.s:3 *ABS*:000000000000003e __SP_H__ +/var/folders/6p/hvps1d6n58jfd6qghfhb96600000gn/T//cchq05jZ.s:4 *ABS*:000000000000003d __SP_L__ +/var/folders/6p/hvps1d6n58jfd6qghfhb96600000gn/T//cchq05jZ.s:5 *ABS*:0000000000000000 __tmp_reg__ +/var/folders/6p/hvps1d6n58jfd6qghfhb96600000gn/T//cchq05jZ.s:6 *ABS*:0000000000000001 __zero_reg__ +/var/folders/6p/hvps1d6n58jfd6qghfhb96600000gn/T//cchq05jZ.s:13 .text:0000000000000000 uart_init + .bss:0000000000000000 tx_buffer +/var/folders/6p/hvps1d6n58jfd6qghfhb96600000gn/T//cchq05jZ.s:336 .bss:0000000000000404 rx_buffer +/var/folders/6p/hvps1d6n58jfd6qghfhb96600000gn/T//cchq05jZ.s:57 .text:000000000000003a uart_putchar +/var/folders/6p/hvps1d6n58jfd6qghfhb96600000gn/T//cchq05jZ.s:121 .text:0000000000000092 uart_getchar +/var/folders/6p/hvps1d6n58jfd6qghfhb96600000gn/T//cchq05jZ.s:157 .text:00000000000000bc __vector_18 +/var/folders/6p/hvps1d6n58jfd6qghfhb96600000gn/T//cchq05jZ.s:247 .text:000000000000013c __vector_19 + +UNDEFINED SYMBOLS +__do_copy_data +__do_clear_bss +__divmodhi4 diff --git a/tpic6b595_shiftout/uart_async.o b/tpic6b595_shiftout/uart_async.o new file mode 100644 index 0000000000000000000000000000000000000000..061328d2e603ef41e3f30ef6636802aa3ad991b8 GIT binary patch literal 6136 zcma)A3v64}89w*=5hr%8lO}yYVRdPF41wKFrM%O~O=${&c2F3wf^iZj@#ff(AEk6- zbxV0pgE+S>P$mi+nzm^g2u*0x7!<_N9O5KUhb=u)9)vtP0&z$-n^#|(iztr8A z)Lrv+_eFKjpX%-lYS)3t!4>YZ)O~BL<6oM04k(pqD76OlN0xQymie-_4T5h&-M{o; zhxN`stheF|E9SSoGuU%S@4i`AsXA-p1yvuVW_^Bkenlg4u#OS4sL=WIjMg!}|7t4K z_crz-gSq%z{F(S%@9LDh!QJX++>*P;eZW29KIuO1zU?l!ZCQz0dsc&umsKmXL0@JI zjkg=mH=b-9X*|%_(2C+vpOPRD_8+KC+ONIRW}B59}V!OpZ3eW)w##2${O zo$kZ2wBtO|op$1nI%%ipNE~Otr@Q~7bq`Ya5Op79eT$_2ZtuUK_zU)3o+gc^B(T~2W6E03X|pWm#agcy0BDJ(7c-bH zOFg0CHX%mX0U>YfaQoOT&9PiDXm4$1MtUd4c|o?F=y*e$BBaP9Va5xX9b*S zlsy)D!rdwm@!T%x!ajq_DAI_~(3U>ZPH`666-PA6M;BXX#HM6!c?Zu#yHR+Od zZFK2}sB}?fnZKhYev)rEl2CjgUV<7>I1B`M0cxW61z3Be(OPPX&8&u5Ty^32&8T5D z;aZb!bL)4&#)n&2O}SRywTSOS#bj`87DhXaYTQi669C`!*@>S;Jz+Ra&!Ot<362U0 z5d2U`kl@EcLIke}2^0KONC&~sg+vH`DWsF&H6dLDzZMcD_>GVl!S9506Z}DlL-0o- zae_;*Qp~ysSeJKkJp;xQSAvcM;%pNP3JDMl3kecjE+j-SA|y<3m5>gCZ9*ahR}1MR z*e;}t;5s2ug6oCE2yPV8O|V0VLvU0G-f~_k!f+V%#95t!Zaf%Jg8Iq}2b*#fz}5%I zw*KjKD}2YX7u8DDD&8%-rE1x7HIuE}Rvb%?F><9ko-ZY*7>2M|^)QZ|&NZ;w>c3*-ijma7r2{KZ zOQkkER;yjPW2A5HiW>$ZeUH}~Ba#01+}a(VzR~VM#+7P0mz`GCT^YP6Cvs&~8_!m= zP)1ah$xP%6IR%gL%uETP&|hwOGO>IyPrseHv1+NDS$lyGU#M!uN`A7K8&8Z)Wy`8i zDo!SvCceuzUv+I_V?wV;`!w~O@y6BT+J;ONvXd20>VtYUh+dGXs?@cWT)C2})@n1Q zLN>LrG@jEdjdjh8=cY@k>P&uY{pfiYo|maieI_TEv z=*z9;d^Oix6InW)5dE>5TE##6N`5ysGg-N9x|$tDTP=I-ltJZOA)Bn`c2!kUZ$Waj zQc+259nX!{CNmS|>~yZpk}pn_;H`VJqod{A&bDrxzc!vNXEDik(L%lmO-}-u@PPea zB>^uUc0BBLS%<6t-e4cga@5w{qtq#j@NmFEMWe^FkKeRs2saPj<3<2>7DM^5hIeT5 z0ZqSQUjXB`-ZutN(eHf%DQ3u8aD&;kqhG0AXqg}0j=GQe4Wk-uK=mf(@C)zZK-%ov z2<+E;4SH|LeEA8-KI&~p_3M2f!KQo$11C@LI~^joen{L=`1#{LyA*F%*fM(;sj zj#-1sQb+Q9KAS?w+KXz=3j5x|7tB`(q?jRWeaoeu!c+e#81eC;E93I@hP2!CZb1OP zxJ@y7hMU%J52|Ae#?Cg-wld`YjLCy~?i-qejxAtW)PRpCfG_p&k2f*Fv4!(+ZRK!m zAuatuOw5A*2srVO_Ty|@CE)!mXc_|Ej|?B@sP?$7 z8N8*g*_IhLU_^uJ^h~Clo78xBu3Qq*dNsCQeVNR7DKl1@xhHyWsYA`H1T&W26CO~Mn^8?Zqk=8?OaW8#KD0Ba zov^X+dD10#H!#OillyIA9S}SO`$K{`m&bq?N!+jb?B5hj|EGZ&i(20SW-Q`)@!@=5 z7tD2d3)pBL7dv&{7tFZ-0p?sz#(C;OHTwJwYV`Yo8Hbwu4NA;dHw)%|jSA-a@b|lk zJ0o_kb5$_cWH&J59zweh)vV!uV6%qz12Yyi=L9p>0pI|}K8AJ~^0(v`<+rQ_JIh(9 z#(oYl?A-T3pM6N|yw|q*?Ayi8d+zH#`?ti-dyi+;;=x2=cnb&fcC>tE6W@!LKj(>m zg_b|8O>U